332adcdd1a
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are assigned only once, after switch_cpus and switch_cpus_1 are constructed.
374 lines
15 KiB
Python
374 lines
15 KiB
Python
# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Lisa Hsu
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from os import getcwd
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from os.path import join as joinpath
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import *
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addToPath('../common')
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def setCPUClass(options):
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atomic = False
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if options.timing:
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class TmpClass(TimingSimpleCPU): pass
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elif options.detailed:
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if not options.caches:
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print "O3 CPU must be used with caches"
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sys.exit(1)
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class TmpClass(DerivO3CPU): pass
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elif options.inorder:
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if not options.caches:
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print "InOrder CPU must be used with caches"
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sys.exit(1)
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class TmpClass(InOrderCPU): pass
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else:
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class TmpClass(AtomicSimpleCPU): pass
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atomic = True
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CPUClass = None
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test_mem_mode = 'atomic'
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if not atomic:
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if options.checkpoint_restore != None or options.fast_forward:
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CPUClass = TmpClass
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class TmpClass(AtomicSimpleCPU): pass
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else:
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test_mem_mode = 'timing'
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return (TmpClass, test_mem_mode, CPUClass)
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def run(options, root, testsys, cpu_class):
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if options.maxtick:
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maxtick = options.maxtick
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elif options.maxtime:
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simtime = m5.ticks.seconds(simtime)
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print "simulating for: ", simtime
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maxtick = simtime
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else:
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maxtick = m5.MaxTick
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if options.checkpoint_dir:
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cptdir = options.checkpoint_dir
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elif m5.options.outdir:
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cptdir = m5.options.outdir
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else:
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cptdir = getcwd()
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if options.fast_forward and options.checkpoint_restore != None:
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fatal("Can't specify both --fast-forward and --checkpoint-restore")
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if options.standard_switch and not options.caches:
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fatal("Must specify --caches when using --standard-switch")
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np = options.num_cpus
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max_checkpoints = options.max_checkpoints
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switch_cpus = None
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if options.prog_intvl:
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for i in xrange(np):
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testsys.cpu[i].progress_interval = options.prog_intvl
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if options.maxinsts:
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for i in xrange(np):
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testsys.cpu[i].max_insts_any_thread = options.maxinsts
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if cpu_class:
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switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
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for i in xrange(np)]
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for i in xrange(np):
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if options.fast_forward:
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testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
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switch_cpus[i].system = testsys
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if not buildEnv['FULL_SYSTEM']:
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switch_cpus[i].workload = testsys.cpu[i].workload
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switch_cpus[i].clock = testsys.cpu[0].clock
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# simulation period
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if options.max_inst:
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switch_cpus[i].max_insts_any_thread = options.max_inst
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testsys.switch_cpus = switch_cpus
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switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
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if options.standard_switch:
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if not options.caches:
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# O3 CPU must have a cache to work.
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print "O3 CPU must be used with caches"
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sys.exit(1)
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switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
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for i in xrange(np)]
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switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
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for i in xrange(np)]
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for i in xrange(np):
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switch_cpus[i].system = testsys
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switch_cpus_1[i].system = testsys
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if not buildEnv['FULL_SYSTEM']:
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switch_cpus[i].workload = testsys.cpu[i].workload
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switch_cpus_1[i].workload = testsys.cpu[i].workload
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switch_cpus[i].clock = testsys.cpu[0].clock
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switch_cpus_1[i].clock = testsys.cpu[0].clock
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# if restoring, make atomic cpu simulate only a few instructions
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if options.checkpoint_restore != None:
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testsys.cpu[i].max_insts_any_thread = 1
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# Fast forward to specified location if we are not restoring
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elif options.fast_forward:
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testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
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# Fast forward to a simpoint (warning: time consuming)
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elif options.simpoint:
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if testsys.cpu[i].workload[0].simpoint == 0:
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fatal('simpoint not found')
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testsys.cpu[i].max_insts_any_thread = \
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testsys.cpu[i].workload[0].simpoint
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# No distance specified, just switch
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else:
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testsys.cpu[i].max_insts_any_thread = 1
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# warmup period
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if options.warmup_insts:
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switch_cpus[i].max_insts_any_thread = options.warmup_insts
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# simulation period
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if options.max_inst:
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switch_cpus_1[i].max_insts_any_thread = options.max_inst
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testsys.switch_cpus = switch_cpus
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testsys.switch_cpus_1 = switch_cpus_1
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switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
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switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
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# set the checkpoint in the cpu before m5.instantiate is called
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if options.take_checkpoints != None and \
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(options.simpoint or options.at_instruction):
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offset = int(options.take_checkpoints)
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# Set an instruction break point
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if options.simpoint:
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for i in xrange(np):
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if testsys.cpu[i].workload[0].simpoint == 0:
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fatal('no simpoint for testsys.cpu[%d].workload[0]', i)
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checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset
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testsys.cpu[i].max_insts_any_thread = checkpoint_inst
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# used for output below
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options.take_checkpoints = checkpoint_inst
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else:
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options.take_checkpoints = offset
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# Set all test cpus with the right number of instructions
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# for the upcoming simulation
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for i in xrange(np):
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testsys.cpu[i].max_insts_any_thread = offset
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checkpoint_dir = None
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if options.checkpoint_restore != None:
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from os.path import isdir, exists
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from os import listdir
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import re
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if not isdir(cptdir):
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fatal("checkpoint dir %s does not exist!", cptdir)
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if options.at_instruction or options.simpoint:
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inst = options.checkpoint_restore
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if options.simpoint:
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# assume workload 0 has the simpoint
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if testsys.cpu[0].workload[0].simpoint == 0:
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fatal('Unable to find simpoint')
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inst += int(testsys.cpu[0].workload[0].simpoint)
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checkpoint_dir = joinpath(cptdir,
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"cpt.%s.%s" % (options.bench, inst))
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if not exists(checkpoint_dir):
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fatal("Unable to find checkpoint directory %s", checkpoint_dir)
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else:
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dirs = listdir(cptdir)
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expr = re.compile('cpt\.([0-9]*)')
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cpts = []
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for dir in dirs:
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match = expr.match(dir)
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if match:
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cpts.append(match.group(1))
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cpts.sort(lambda a,b: cmp(long(a), long(b)))
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cpt_num = options.checkpoint_restore
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if cpt_num > len(cpts):
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fatal('Checkpoint %d not found', cpt_num)
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## Adjust max tick based on our starting tick
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maxtick = maxtick - int(cpts[cpt_num - 1])
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checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])
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m5.instantiate(checkpoint_dir)
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if options.standard_switch or cpu_class:
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if options.standard_switch:
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print "Switch at instruction count:%s" % \
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str(testsys.cpu[0].max_insts_any_thread)
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exit_event = m5.simulate()
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elif cpu_class and options.fast_forward:
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print "Switch at instruction count:%s" % \
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str(testsys.cpu[0].max_insts_any_thread)
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exit_event = m5.simulate()
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else:
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print "Switch at curTick count:%s" % str(10000)
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exit_event = m5.simulate(10000)
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print "Switched CPUS @ tick %s" % (m5.curTick())
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# when you change to Timing (or Atomic), you halt the system
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# given as argument. When you are finished with the system
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# changes (including switchCpus), you must resume the system
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# manually. You DON'T need to resume after just switching
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# CPUs if you haven't changed anything on the system level.
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m5.changeToTiming(testsys)
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m5.switchCpus(switch_cpu_list)
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m5.resume(testsys)
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if options.standard_switch:
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print "Switch at instruction count:%d" % \
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(testsys.switch_cpus[0].max_insts_any_thread)
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#warmup instruction count may have already been set
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if options.warmup_insts:
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exit_event = m5.simulate()
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else:
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exit_event = m5.simulate(options.warmup)
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print "Switching CPUS @ tick %s" % (m5.curTick())
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print "Simulation ends instruction count:%d" % \
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(testsys.switch_cpus_1[0].max_insts_any_thread)
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m5.drain(testsys)
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m5.switchCpus(switch_cpu_list1)
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m5.resume(testsys)
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num_checkpoints = 0
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exit_cause = ''
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# If we're taking and restoring checkpoints, use checkpoint_dir
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# option only for finding the checkpoints to restore from. This
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# lets us test checkpointing by restoring from one set of
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# checkpoints, generating a second set, and then comparing them.
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if options.take_checkpoints and options.checkpoint_restore:
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if m5.options.outdir:
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cptdir = m5.options.outdir
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else:
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cptdir = getcwd()
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# Checkpoints being taken via the command line at <when> and at
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# subsequent periods of <period>. Checkpoint instructions
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# received from the benchmark running are ignored and skipped in
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# favor of command line checkpoint instructions.
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if options.take_checkpoints != None :
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if options.at_instruction or options.simpoint:
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checkpoint_inst = int(options.take_checkpoints)
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# maintain correct offset if we restored from some instruction
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if options.checkpoint_restore != None:
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checkpoint_inst += options.checkpoint_restore
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print "Creating checkpoint at inst:%d" % (checkpoint_inst)
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exit_event = m5.simulate()
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print "exit cause = %s" % (exit_event.getCause())
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# skip checkpoint instructions should they exist
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while exit_event.getCause() == "checkpoint":
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exit_event = m5.simulate()
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if exit_event.getCause() == \
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"a thread reached the max instruction count":
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m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \
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(options.bench, checkpoint_inst)))
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print "Checkpoint written."
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num_checkpoints += 1
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if exit_event.getCause() == "user interrupt received":
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exit_cause = exit_event.getCause();
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else:
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when, period = options.take_checkpoints.split(",", 1)
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when = int(when)
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period = int(period)
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exit_event = m5.simulate(when)
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while exit_event.getCause() == "checkpoint":
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exit_event = m5.simulate(when - m5.curTick())
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if exit_event.getCause() == "simulate() limit reached":
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m5.checkpoint(joinpath(cptdir, "cpt.%d"))
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num_checkpoints += 1
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sim_ticks = when
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exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
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while num_checkpoints < max_checkpoints and \
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exit_event.getCause() == "simulate() limit reached":
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if (sim_ticks + period) > maxtick:
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exit_event = m5.simulate(maxtick - sim_ticks)
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exit_cause = exit_event.getCause()
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break
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else:
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exit_event = m5.simulate(period)
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sim_ticks += period
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while exit_event.getCause() == "checkpoint":
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exit_event = m5.simulate(sim_ticks - m5.curTick())
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if exit_event.getCause() == "simulate() limit reached":
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m5.checkpoint(joinpath(cptdir, "cpt.%d"))
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num_checkpoints += 1
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if exit_event.getCause() != "simulate() limit reached":
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exit_cause = exit_event.getCause();
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else: # no checkpoints being taken via this script
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if options.fast_forward:
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m5.stats.reset()
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print "**** REAL SIMULATION ****"
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exit_event = m5.simulate(maxtick)
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while exit_event.getCause() == "checkpoint":
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m5.checkpoint(joinpath(cptdir, "cpt.%d"))
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num_checkpoints += 1
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if num_checkpoints == max_checkpoints:
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exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
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break
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exit_event = m5.simulate(maxtick - m5.curTick())
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exit_cause = exit_event.getCause()
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if exit_cause == '':
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exit_cause = exit_event.getCause()
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print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)
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if options.checkpoint_at_end:
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m5.checkpoint(joinpath(cptdir, "cpt.%d"))
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