gem5/ext/mcpat/cacti/htree2.h
Yasuko Eckert 0deef376d9 ext: McPAT interface changes and fixes
This patch includes software engineering changes and some generic bug fixes
Joel Hestness and Yasuko Eckert made to McPAT 0.8. There are still known
issues/concernts we did not have a chance to address in this patch.

High-level changes in this patch include:
 1) Making XML parsing modular and hierarchical:
   - Shift parsing responsibility into the components
   - Read XML in a (mostly) context-free recursive manner so that McPAT input
     files can contain arbitrary component hierarchies
 2) Making power, energy, and area calculations a hierarchical and recursive
    process
   - Components track their subcomponents and recursively call compute
     functions in stages
   - Make C++ object hierarchy reflect inheritance of classes of components
     with similar structures
   - Simplify computeArea() and computeEnergy() functions to eliminate
     successive calls to calculate separate TDP vs. runtime energy
   - Remove Processor component (now unnecessary) and introduce a more abstract
     System component
 3) Standardizing McPAT output across all components
   - Use a single, common data structure for storing and printing McPAT output
   - Recursively call print functions through component hierarchy
 4) For caches, allow splitting data array and tag array reads and writes for
    better accuracy
 5) Improving the usability of CACTI by printing more helpful warning and error
    messages
 6) Minor: Impose more rigorous code style for clarity (more work still to be
    done)
Overall, these changes greatly reduce the amount of replicated code, and they
improve McPAT runtime and decrease memory footprint.
2014-06-03 13:32:59 -07:00

101 lines
3.6 KiB
C++

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* McPAT/CACTI
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#ifndef __HTREE2_H__
#define __HTREE2_H__
#include "assert.h"
#include "basic_circuit.h"
#include "cacti_interface.h"
#include "component.h"
#include "parameter.h"
#include "subarray.h"
#include "wire.h"
// leakge power includes entire htree in a bank (when uca_tree == false)
// leakge power includes only part to one bank when uca_tree == true
class Htree2 : public Component {
public:
Htree2(enum Wire_type wire_model,
double mat_w, double mat_h, int add, int data_in, int search_data_in, int data_out, int search_data_out, int bl, int wl,
enum Htree_type h_type, bool uca_tree_ = false, bool search_tree_ = false,
TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
~Htree2() {};
void in_htree();
void out_htree();
// repeaters only at h-tree nodes
void limited_in_htree();
void limited_out_htree();
void input_nand(double s1, double s2, double l);
void output_buffer(double s1, double s2, double l);
double in_rise_time, out_rise_time;
void set_in_rise_time(double rt) {
in_rise_time = rt;
}
double max_unpipelined_link_delay;
powerDef power_bit;
private:
double wire_bw;
double init_wire_bw; // bus width at root
enum Htree_type tree_type;
double htree_hnodes;
double htree_vnodes;
double mat_width;
double mat_height;
int add_bits;
int data_in_bits;
int search_data_in_bits;
int data_out_bits;
int search_data_out_bits;
int ndbl, ndwl;
bool uca_tree; // should have full bandwidth to access all banks in the array simultaneously
bool search_tree;
enum Wire_type wt;
double min_w_nmos;
double min_w_pmos;
TechnologyParameter::DeviceType *deviceType;
};
#endif