1210 lines
139 KiB
Text
1210 lines
139 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.770368 # Number of seconds simulated
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sim_ticks 770368138000 # Number of ticks simulated
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final_tick 770368138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 139680 # Simulator instruction rate (inst/s)
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host_op_rate 150484 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 69667014 # Simulator tick rate (ticks/s)
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host_mem_usage 312136 # Number of bytes of host memory used
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host_seconds 11057.86 # Real time elapsed on the host
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sim_insts 1544563024 # Number of instructions simulated
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sim_ops 1664032416 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 65792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 238160448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 63905024 # Number of bytes read from this memory
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system.physmem.bytes_read::total 302131264 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 65792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 65792 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 104870272 # Number of bytes written to this memory
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system.physmem.bytes_written::total 104870272 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1028 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3721257 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 998516 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 4720801 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1638598 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1638598 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 85403 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 309151477 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 82953877 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 392190758 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 85403 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 85403 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 136130074 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 136130074 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 136130074 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 85403 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 309151477 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 82953877 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 528320833 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 4720801 # Number of read requests accepted
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system.physmem.writeReqs 1638598 # Number of write requests accepted
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system.physmem.readBursts 4720801 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1638598 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 301683008 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 448256 # Total number of bytes read from write queue
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system.physmem.bytesWritten 104867648 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 302131264 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 104870272 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 7004 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 296472 # Per bank write bursts
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system.physmem.perBankRdBursts::1 294660 # Per bank write bursts
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system.physmem.perBankRdBursts::2 288575 # Per bank write bursts
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system.physmem.perBankRdBursts::3 292960 # Per bank write bursts
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system.physmem.perBankRdBursts::4 290749 # Per bank write bursts
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system.physmem.perBankRdBursts::5 289530 # Per bank write bursts
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system.physmem.perBankRdBursts::6 284828 # Per bank write bursts
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system.physmem.perBankRdBursts::7 280913 # Per bank write bursts
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system.physmem.perBankRdBursts::8 297084 # Per bank write bursts
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system.physmem.perBankRdBursts::9 304004 # Per bank write bursts
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system.physmem.perBankRdBursts::10 295272 # Per bank write bursts
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system.physmem.perBankRdBursts::11 301446 # Per bank write bursts
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system.physmem.perBankRdBursts::12 303554 # Per bank write bursts
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system.physmem.perBankRdBursts::13 302544 # Per bank write bursts
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system.physmem.perBankRdBursts::14 297853 # Per bank write bursts
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system.physmem.perBankRdBursts::15 293353 # Per bank write bursts
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system.physmem.perBankWrBursts::0 103842 # Per bank write bursts
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system.physmem.perBankWrBursts::1 101847 # Per bank write bursts
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system.physmem.perBankWrBursts::2 99335 # Per bank write bursts
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system.physmem.perBankWrBursts::3 100097 # Per bank write bursts
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system.physmem.perBankWrBursts::4 99287 # Per bank write bursts
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system.physmem.perBankWrBursts::5 99035 # Per bank write bursts
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system.physmem.perBankWrBursts::6 102669 # Per bank write bursts
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system.physmem.perBankWrBursts::7 104576 # Per bank write bursts
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system.physmem.perBankWrBursts::8 105230 # Per bank write bursts
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system.physmem.perBankWrBursts::9 104522 # Per bank write bursts
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system.physmem.perBankWrBursts::10 102176 # Per bank write bursts
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system.physmem.perBankWrBursts::11 103126 # Per bank write bursts
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system.physmem.perBankWrBursts::12 103102 # Per bank write bursts
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system.physmem.perBankWrBursts::13 102725 # Per bank write bursts
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system.physmem.perBankWrBursts::14 104361 # Per bank write bursts
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system.physmem.perBankWrBursts::15 102627 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 770367991500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 4720801 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1638598 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 2785137 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1045602 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 327608 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 232677 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 151173 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 83865 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 38451 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 23803 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 18009 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 4245 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1721 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 821 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 446 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 23398 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 25057 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 60199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 75747 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 85433 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 93667 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 99999 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 103866 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 105492 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 106217 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 106151 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 106693 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 108356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 111353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 114123 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 105280 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 101866 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 101152 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 2626 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1015 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 458 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 215 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 13 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 4291005 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 94.744514 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 78.906714 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 101.391830 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 3416666 79.62% 79.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 676199 15.76% 95.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 96816 2.26% 97.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 35217 0.82% 98.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 22960 0.54% 98.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 11971 0.28% 99.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 7013 0.16% 99.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 5097 0.12% 99.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 19066 0.44% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 4291005 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 98697 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 47.759952 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 32.369236 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 98.446894 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-255 96231 97.50% 97.50% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::256-511 1192 1.21% 98.71% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::512-767 746 0.76% 99.47% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::768-1023 392 0.40% 99.86% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-1279 102 0.10% 99.97% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::1280-1535 22 0.02% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1536-1791 3 0.00% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1792-2047 3 0.00% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::3584-3839 2 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 98697 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 98697 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.601893 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.567781 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.107607 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 72640 73.60% 73.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 1756 1.78% 75.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 18593 18.84% 94.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 3904 3.96% 98.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 1031 1.04% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 392 0.40% 99.61% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::22 184 0.19% 99.80% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 91 0.09% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 55 0.06% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 31 0.03% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 17 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 98697 # Writes before turning the bus around for reads
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|
system.physmem.totQLat 131099404549 # Total ticks spent queuing
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system.physmem.totMemAccLat 219483098299 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 23568985000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 27811.85 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 46561.85 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 391.61 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 136.13 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 392.19 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 136.13 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 4.12 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 1707890 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 353447 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 21.57 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 121138.49 # Average gap between requests
|
|
system.physmem.pageHitRate 32.45 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 16077957840 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 8772695250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 18085189200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 5253161040 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 410294660580 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 102310835250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 611110917000 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 793.275483 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 167665323859 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 25724140000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 576975365641 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 16361828280 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 8927584875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 18681803400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 5364480960 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 411044339970 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 101653218750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 612349674075 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 794.883504 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 166565047661 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 25724140000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 578076556839 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 286273758 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 223402774 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 14629982 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 157694112 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 150348271 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 95.341715 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 16640713 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
|
system.cpu.numCycles 1540736277 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 13925194 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 2067435227 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 286273758 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 166988984 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 1512088964 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 29284609 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 656921798 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 960 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 1540658157 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.437628 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.228937 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 458280922 29.75% 29.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 465413379 30.21% 59.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 101412163 6.58% 66.54% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 515551693 33.46% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1540658157 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.185803 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.341849 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 74641640 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 543291473 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 849963258 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 58120186 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 14641600 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 42202380 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 756 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 2037144212 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 52474408 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 14641600 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 139712786 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 462567620 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 14938 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 837837029 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 85884184 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 1976322026 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 26747258 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 45146985 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 125259 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1471751 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 25027790 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 1985779948 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 9127891240 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 2432801848 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 139 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 310881003 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 157 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 151 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 111429534 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 542545285 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 199304809 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 26862690 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 28866621 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 1947900293 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 1857514523 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 13512332 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 283868093 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 647012526 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1540658157 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.205663 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.150942 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 587771265 38.15% 38.15% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 326011747 21.16% 59.31% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 378176386 24.55% 83.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 219651217 14.26% 98.11% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 29041357 1.88% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 6185 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1540658157 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 166072420 40.95% 40.95% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 2002 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 191493456 47.22% 88.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 47936528 11.82% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1138226056 61.28% 61.28% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 801017 0.04% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 532163815 28.65% 89.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 186323583 10.03% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 1857514523 # Type of FU issued
|
|
system.cpu.iq.rate 1.205602 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 405504406 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.218305 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5674703700 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2231781287 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1805692489 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 241 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2263018794 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 17823551 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 84238951 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 66626 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 13177 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 24457764 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 4548930 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4887285 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 14641600 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 25334604 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1297189 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 1947900591 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 542545285 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 199304809 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 159299 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 1136868 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 13177 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 7700706 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 8703944 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 16404650 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1827845280 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 516985272 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 29669243 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 82 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 698740184 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 229542491 # Number of branches executed
|
|
system.cpu.iew.exec_stores 181754912 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.186345 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1808718850 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1805692560 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1169243952 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1689620594 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.171967 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.692016 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 257974948 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 14629278 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1501179372 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.108483 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.025812 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 920919616 61.35% 61.35% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 250623048 16.70% 78.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 110074231 7.33% 85.37% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 55314266 3.68% 89.06% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 29240414 1.95% 91.01% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 34051194 2.27% 93.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 24724968 1.65% 94.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 18102388 1.21% 96.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 58129247 3.87% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1501179372 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 633153379 # Number of memory references committed
|
|
system.cpu.commit.loads 458306334 # Number of loads committed
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
system.cpu.commit.branches 213462427 # Number of branches committed
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 58129247 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 3365056908 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 3883498749 # The number of ROB writes
|
|
system.cpu.timesIdled 826 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 78120 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.997522 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.997522 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.002484 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.002484 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 2175832090 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1261554579 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 42 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 53 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 6965806989 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 551858746 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 675847493 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 17004655 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.964606 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 638048144 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 17005167 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 37.520840 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 78823500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.964606 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1335675523 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1335675523 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 469328921 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 469328921 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 168719105 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 168719105 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 638048026 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 638048026 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 638048026 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 638048026 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 17420086 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 17420086 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3866942 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 3866942 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 21287028 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 21287028 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 21287030 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 21287030 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 415615381500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 415615381500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149888945711 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 149888945711 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 398000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 398000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 565504327211 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 565504327211 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 565504327211 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 565504327211 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 486749007 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 486749007 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 659335054 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 659335054 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 659335056 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 659335056 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035789 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.035789 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23858.400096 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 23858.400096 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38761.622417 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38761.622417 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.677802 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 26565.677802 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26565.675306 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 26565.675306 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 20779473 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 3451346 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 944816 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 67198 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.993143 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 51.360844 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 4837348 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 4837348 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3152457 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 3152457 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129405 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1129405 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4281862 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4281862 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4281862 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4281862 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267629 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 14267629 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737537 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 2737537 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 17005166 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 17005166 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 17005167 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 17005167 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335438494000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 335438494000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116411117573 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 116411117573 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451849611573 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 451849611573 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451849679573 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 451849679573 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029312 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029312 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23510.458115 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23510.458115 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42524.034405 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42524.034405 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26571.314363 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26571.314363 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26571.316799 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26571.316799 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 582 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 445.815002 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 656920172 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1070 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 613944.085981 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 445.815002 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.870732 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.870732 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 1313844660 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 1313844660 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 656920172 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 656920172 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 656920172 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 656920172 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 656920172 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 656920172 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1623 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1623 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1623 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1623 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1623 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1623 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 104193985 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 104193985 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 104193985 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 104193985 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 104193985 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 104193985 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 656921795 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 656921795 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 656921795 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 656921795 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 656921795 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 656921795 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64198.388786 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 64198.388786 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 64198.388786 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 64198.388786 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 17135 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 748 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 90.184211 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 553 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 553 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 553 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 553 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 553 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 553 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1070 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1070 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1070 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1070 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1070 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1070 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75689488 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 75689488 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75689488 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 75689488 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75689488 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 75689488 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70737.839252 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70737.839252 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70737.839252 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 70737.839252 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 11618797 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 11638031 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 14266 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 4656553 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 4712696 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 16129.917520 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 27373018 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 4728623 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 5.788793 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 29478535500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 5230.477637 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.698420 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 7539.676601 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3341.064863 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.319243 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001141 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.460185 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.203922 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.984492 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 811 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15116 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 615 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 195 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2303 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1194 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9259 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1857 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049500 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922607 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 551304223 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 551304223 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 4837348 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 4837348 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1752512 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1752512 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 42 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 42 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11483403 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 11483403 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 42 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 13235915 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 13235957 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 42 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 13235915 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 13235957 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 985072 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 985072 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1028 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 1028 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2784180 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 2784180 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1028 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3769252 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 3770280 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1028 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3769252 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 3770280 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99860242499 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 99860242499 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 74336500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 74336500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 238301833000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 238301833000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 74336500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 338162075499 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 338236411999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 74336500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 338162075499 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 338236411999 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 4837348 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 4837348 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737584 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 2737584 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1070 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1070 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14267583 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 14267583 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1070 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 17005167 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 17006237 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1070 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 17005167 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 17006237 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359833 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.359833 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.960748 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.960748 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.195140 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.195140 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960748 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.221653 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.221700 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960748 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.221653 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.221700 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101373.546806 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101373.546806 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72311.770428 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72311.770428 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85591.388847 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85591.388847 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72311.770428 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89715.963671 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 89711.218265 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72311.770428 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89715.963671 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 89711.218265 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 184 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1638598 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1638598 # number of writebacks
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3903 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 3903 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 44598 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 44598 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 48501 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 48501 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 48501 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 48501 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 100273 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 100273 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1001612 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 1001612 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981169 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 981169 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1028 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1028 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2739582 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2739582 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1028 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3720751 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 3721779 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1028 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3720751 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1001612 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 4723391 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72748405464 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72748405464 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93609887499 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93609887499 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68168500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68168500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 219013270500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 219013270500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68168500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312623157999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 312691326499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68168500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312623157999 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72748405464 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 385439731963 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358407 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358407 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.960748 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.192014 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.192014 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.218848 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.277745 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72631.323770 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95406.487057 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95406.487057 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66311.770428 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66311.770428 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79944.046391 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79944.046391 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84016.629278 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81602.334417 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 14268653 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 6475946 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 15220389 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 1280497 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 2737584 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 2737584 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1070 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267583 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2718 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993396 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 50996114 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397921024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 1397989504 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 5993194 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 40004669 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.149812 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.356887 # Request fanout histogram
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|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 34011476 85.02% 85.02% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 5993193 14.98% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 40004669 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 21843087497 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1605000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 25507754991 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 3739456 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1638598 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 3064906 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 981345 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 981345 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 3739456 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14145106 # Packet count per connected master and slave (bytes)
|
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system.membus.pkt_count::total 14145106 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407001536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 407001536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 9424305 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 9424305 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 9424305 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 17323735553 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 25676323677 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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