gem5/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
Ali Saidi 5b1970d1a3 Add regression for SPARC "hard" instruction test. Only runs in simple-atomic right now since we don't have cache support for
the atomic instructions.

--HG--
extra : convert_revision : b7013e6963885dfe2b4630ac175e24ddad6d42a6
2007-03-06 15:57:28 -05:00

68 lines
1 KiB
INI

[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
clock=1
cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
simulate_stalls=false
system=system
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
egid=100
env=
euid=100
executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]