gem5/src/arch/x86/isa/formats
2007-03-29 17:57:19 +00:00
..
basic.isa Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are. 2007-03-21 19:19:53 +00:00
error.isa Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are. 2007-03-21 19:19:53 +00:00
formats.isa Start implementing groups of instructions which do the same thing on different sets of inputs. 2007-03-21 21:07:43 +00:00
multi.isa Made the MultiOp format do a little more. It now sets up single microop instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support. 2007-03-29 17:57:19 +00:00
unimp.isa Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are. 2007-03-21 19:19:53 +00:00
unknown.isa Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86. 2007-03-15 02:47:42 +00:00