95a0b18431
Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby.
300 lines
9.9 KiB
Text
300 lines
9.9 KiB
Text
/*
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* Copyright (c) 2009-2013 Mark D. Hill and David A. Wood
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* Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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machine(DMA, "DMA Controller")
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: DMASequencer * dma_sequencer;
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Cycles request_latency := 14;
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Cycles response_latency := 14;
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MessageBuffer * responseFromDir, network="From", virtual_network="2",
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ordered="false", vnet_type="response";
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MessageBuffer * reqToDir, network="To", virtual_network="1",
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ordered="false", vnet_type="request";
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MessageBuffer * respToDir, network="To", virtual_network="2",
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ordered="false", vnet_type="dmaresponse";
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{
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state_declaration(State, desc="DMA states", default="DMA_State_READY") {
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READY, AccessPermission:Invalid, desc="Ready to accept a new request";
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BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
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BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
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}
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enumeration(Event, desc="DMA events") {
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ReadRequest, desc="A new read request";
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WriteRequest, desc="A new write request";
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Data, desc="Data from a DMA memory read";
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DMA_Ack, desc="DMA write to memory completed";
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Inv_Ack, desc="Invalidation Ack from a sharer";
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All_Acks, desc="All acks received";
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}
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structure(TBE, desc="...") {
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Address address, desc="Physical address";
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int NumAcks, default="0", desc="Number of Acks pending";
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DataBlock DataBlk, desc="Data";
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}
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structure(TBETable, external = "yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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MessageBuffer mandatoryQueue, ordered="false";
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MessageBuffer triggerQueue, ordered="true";
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TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
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State cur_state;
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void set_tbe(TBE b);
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void unset_tbe();
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State getState(TBE tbe, Address addr) {
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return cur_state;
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}
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void setState(TBE tbe, Address addr, State state) {
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cur_state := state;
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}
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AccessPermission getAccessPermission(Address addr) {
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Address addr, State state) {
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}
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DataBlock getDataBlock(Address addr), return_by_ref="yes" {
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error("DMA Controller does not support getDataBlock().\n");
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}
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out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="...");
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out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
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out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");
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in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
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if (dmaRequestQueue_in.isReady()) {
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peek(dmaRequestQueue_in, SequencerMsg) {
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if (in_msg.Type == SequencerRequestType:LD ) {
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trigger(Event:ReadRequest, in_msg.LineAddress,
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TBEs[in_msg.LineAddress]);
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} else if (in_msg.Type == SequencerRequestType:ST) {
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trigger(Event:WriteRequest, in_msg.LineAddress,
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TBEs[in_msg.LineAddress]);
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} else {
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error("Invalid request type");
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}
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}
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}
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}
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in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
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if (dmaResponseQueue_in.isReady()) {
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peek( dmaResponseQueue_in, ResponseMsg) {
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if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
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trigger(Event:DMA_Ack, makeLineAddress(in_msg.Addr),
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TBEs[makeLineAddress(in_msg.Addr)]);
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} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE ||
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in_msg.Type == CoherenceResponseType:DATA) {
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trigger(Event:Data, makeLineAddress(in_msg.Addr),
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TBEs[makeLineAddress(in_msg.Addr)]);
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} else if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:Inv_Ack, makeLineAddress(in_msg.Addr),
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TBEs[makeLineAddress(in_msg.Addr)]);
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} else {
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error("Invalid response type");
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}
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}
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}
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}
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// Trigger Queue
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in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
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if (triggerQueue_in.isReady()) {
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peek(triggerQueue_in, TriggerMsg) {
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if (in_msg.Type == TriggerType:ALL_ACKS) {
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trigger(Event:All_Acks, in_msg.Addr, TBEs[in_msg.Addr]);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
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peek(dmaRequestQueue_in, SequencerMsg) {
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enqueue(reqToDirectory_out, RequestMsg, request_latency) {
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out_msg.Addr := in_msg.PhysicalAddress;
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out_msg.Type := CoherenceRequestType:DMA_READ;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Requestor := machineID;
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out_msg.RequestorMachine := MachineType:DMA;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
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peek(dmaRequestQueue_in, SequencerMsg) {
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enqueue(reqToDirectory_out, RequestMsg, request_latency) {
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out_msg.Addr := in_msg.PhysicalAddress;
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out_msg.Type := CoherenceRequestType:DMA_WRITE;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Requestor := machineID;
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out_msg.RequestorMachine := MachineType:DMA;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
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dma_sequencer.ackCallback();
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}
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action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
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assert(is_valid(tbe));
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if (tbe.NumAcks == 0) {
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enqueue(triggerQueue_out, TriggerMsg) {
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out_msg.Addr := address;
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out_msg.Type := TriggerType:ALL_ACKS;
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}
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}
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}
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action(u_updateAckCount, "u", desc="Update ack count") {
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peek(dmaResponseQueue_in, ResponseMsg) {
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assert(is_valid(tbe));
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tbe.NumAcks := tbe.NumAcks - in_msg.Acks;
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}
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}
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action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") {
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enqueue(respToDirectory_out, ResponseMsg, response_latency) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:DMA;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(p_popRequestQueue, "p", desc="Pop request queue") {
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dmaRequestQueue_in.dequeue();
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}
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action(p_popResponseQueue, "\p", desc="Pop request queue") {
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dmaResponseQueue_in.dequeue();
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}
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action(p_popTriggerQueue, "pp", desc="Pop trigger queue") {
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triggerQueue_in.dequeue();
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}
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action(t_updateTBEData, "t", desc="Update TBE Data") {
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peek(dmaResponseQueue_in, ResponseMsg) {
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assert(is_valid(tbe));
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tbe.DataBlk := in_msg.DataBlk;
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}
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}
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action(d_dataCallbackFromTBE, "/d", desc="data callback with data from TBE") {
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assert(is_valid(tbe));
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dma_sequencer.dataCallback(tbe.DataBlk);
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}
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action(v_allocateTBE, "v", desc="Allocate TBE entry") {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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}
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action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
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TBEs.deallocate(address);
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unset_tbe();
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}
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transition(READY, ReadRequest, BUSY_RD) {
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s_sendReadRequest;
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v_allocateTBE;
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p_popRequestQueue;
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}
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transition(BUSY_RD, Inv_Ack) {
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u_updateAckCount;
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o_checkForCompletion;
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p_popResponseQueue;
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}
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transition(BUSY_RD, Data, READY) {
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t_updateTBEData;
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d_dataCallbackFromTBE;
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w_deallocateTBE;
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//u_updateAckCount;
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//o_checkForCompletion;
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p_popResponseQueue;
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}
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transition(BUSY_RD, All_Acks, READY) {
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d_dataCallbackFromTBE;
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//u_sendExclusiveUnblockToDir;
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w_deallocateTBE;
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p_popTriggerQueue;
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}
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transition(READY, WriteRequest, BUSY_WR) {
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s_sendWriteRequest;
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v_allocateTBE;
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p_popRequestQueue;
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}
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transition(BUSY_WR, Inv_Ack) {
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u_updateAckCount;
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o_checkForCompletion;
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p_popResponseQueue;
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}
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transition(BUSY_WR, DMA_Ack) {
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u_updateAckCount; // actually increases
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o_checkForCompletion;
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p_popResponseQueue;
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}
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transition(BUSY_WR, All_Acks, READY) {
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a_ackCallback;
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u_sendExclusiveUnblockToDir;
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w_deallocateTBE;
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p_popTriggerQueue;
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}
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}
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