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gem5/src/arch/sparc/faults.cc
Gabe Black 6f4bd2c1da ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 00:07:20 -07:00

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/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
* Kevin Lim
*/
#include <algorithm>
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
#include "arch/sparc/process.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#endif
using namespace std;
namespace SparcISA
{
template<> SparcFaultBase::FaultVals
SparcFault<PowerOnReset>::vals =
{"power_on_reset", 0x001, 0, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<WatchDogReset>::vals =
{"watch_dog_reset", 0x002, 120, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<ExternallyInitiatedReset>::vals =
{"externally_initiated_reset", 0x003, 110, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<SoftwareInitiatedReset>::vals =
{"software_initiated_reset", 0x004, 130, {SH, SH, H}};
template<> SparcFaultBase::FaultVals
SparcFault<REDStateException>::vals =
{"RED_state_exception", 0x005, 1, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<StoreError>::vals =
{"store_error", 0x007, 201, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionAccessException>::vals =
{"instruction_access_exception", 0x008, 300, {H, H, H}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<InstructionAccessMMUMiss>::vals =
{"inst_mmu", 0x009, 2, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<InstructionAccessError>::vals =
{"instruction_access_error", 0x00A, 400, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<IllegalInstruction>::vals =
{"illegal_instruction", 0x010, 620, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<PrivilegedOpcode>::vals =
{"privileged_opcode", 0x011, 700, {P, SH, SH}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<UnimplementedLDD>::vals =
{"unimp_ldd", 0x012, 6, {H, H, H}};*/
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<UnimplementedSTD>::vals =
{"unimp_std", 0x013, 6, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<FpDisabled>::vals =
{"fp_disabled", 0x020, 800, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FpExceptionIEEE754>::vals =
{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FpExceptionOther>::vals =
{"fp_exception_other", 0x022, 1110, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<TagOverflow>::vals =
{"tag_overflow", 0x023, 1400, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<CleanWindow>::vals =
{"clean_window", 0x024, 1010, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<DivisionByZero>::vals =
{"division_by_zero", 0x028, 1500, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InternalProcessorError>::vals =
{"internal_processor_error", 0x029, 4, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionInvalidTSBEntry>::vals =
{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<DataInvalidTSBEntry>::vals =
{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<DataAccessException>::vals =
{"data_access_exception", 0x030, 1201, {H, H, H}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<DataAccessMMUMiss>::vals =
{"data_mmu", 0x031, 12, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<DataAccessError>::vals =
{"data_access_error", 0x032, 1210, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<DataAccessProtection>::vals =
{"data_access_protection", 0x033, 1207, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<MemAddressNotAligned>::vals =
{"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<LDDFMemAddressNotAligned>::vals =
{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<STDFMemAddressNotAligned>::vals =
{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<PrivilegedAction>::vals =
{"privileged_action", 0x037, 1110, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<LDQFMemAddressNotAligned>::vals =
{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<STQFMemAddressNotAligned>::vals =
{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionRealTranslationMiss>::vals =
{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<DataRealTranslationMiss>::vals =
{"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
SparcFault<AsyncDataError>::vals =
{"async_data", 0x040, 2, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
SparcFault<InterruptLevelN>::vals =
{"interrupt_level_n", 0x040, 0, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<HstickMatch>::vals =
{"hstick_match", 0x05E, 1601, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<TrapLevelZero>::vals =
{"trap_level_zero", 0x05F, 202, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<InterruptVector>::vals =
{"interrupt_vector", 0x060, 2630, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<PAWatchpoint>::vals =
{"PA_watchpoint", 0x061, 1209, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<VAWatchpoint>::vals =
{"VA_watchpoint", 0x062, 1120, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<FastInstructionAccessMMUMiss>::vals =
{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<FastDataAccessMMUMiss>::vals =
{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FastDataAccessProtection>::vals =
{"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<InstructionBreakpoint>::vals =
{"instruction_break", 0x076, 610, {H, H, H}};
template<> SparcFaultBase::FaultVals
SparcFault<CpuMondo>::vals =
{"cpu_mondo", 0x07C, 1608, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<DevMondo>::vals =
{"dev_mondo", 0x07D, 1611, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<ResumableError>::vals =
{"resume_error", 0x07E, 3330, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<SpillNNormal>::vals =
{"spill_n_normal", 0x080, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<SpillNOther>::vals =
{"spill_n_other", 0x0A0, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FillNNormal>::vals =
{"fill_n_normal", 0x0C0, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<FillNOther>::vals =
{"fill_n_other", 0x0E0, 900, {P, P, H}};
template<> SparcFaultBase::FaultVals
SparcFault<TrapInstruction>::vals =
{"trap_instruction", 0x100, 1602, {P, P, H}};
/**
* This causes the thread context to enter RED state. This causes the side
* effects which go with entering RED state because of a trap.
*/
void enterREDState(ThreadContext *tc)
{
//@todo Disable the mmu?
//@todo Disable watchpoints?
MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
//HPSTATE.red = 1
HPSTATE |= (1 << 5);
//HPSTATE.hpriv = 1
HPSTATE |= (1 << 2);
tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
//PSTATE.priv is set to 1 here. The manual says it should be 0, but
//Legion sets it to 1.
MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
PSTATE |= (1 << 2);
tc->setMiscReg(MISCREG_PSTATE, PSTATE);
}
/**
* This sets everything up for a RED state trap except for actually jumping to
* the handler.
*/
void doREDFault(ThreadContext *tc, TrapType tt)
{
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
//MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
//MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState();
TL++;
Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
//set TSTATE.gl to gl
replaceBits(TSTATE, 42, 40, GL);
//set TSTATE.ccr to ccr
replaceBits(TSTATE, 39, 32, CCR);
//set TSTATE.asi to asi
replaceBits(TSTATE, 31, 24, ASI);
//set TSTATE.pstate to pstate
replaceBits(TSTATE, 20, 8, PSTATE);
//set TSTATE.cwp to cwp
replaceBits(TSTATE, 4, 0, CWP);
//Write back TSTATE
tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
//set TPC to PC
tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
//set TNPC to NPC
tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
//set HTSTATE.hpstate to hpstate
tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
//TT = trap type;
tc->setMiscRegNoEffect(MISCREG_TT, tt);
//Update GL
tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
PSTATE |= (1 << 4); //set PSTATE.pef to 1
tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
//set HPSTATE.red to 1
HPSTATE |= (1 << 5);
//set HPSTATE.hpriv to 1
HPSTATE |= (1 << 2);
//set HPSTATE.ibe to 0
HPSTATE &= ~(1 << 10);
//set HPSTATE.tlz to 0
HPSTATE &= ~(1 << 0);
tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
bool changedCWP = true;
if(tt == 0x24)
CWP++;
else if(0x80 <= tt && tt <= 0xbf)
CWP += (CANSAVE + 2);
else if(0xc0 <= tt && tt <= 0xff)
CWP--;
else
changedCWP = false;
if(changedCWP)
{
CWP = (CWP + NWindows) % NWindows;
tc->setMiscReg(MISCREG_CWP, CWP);
}
}
/**
* This sets everything up for a normal trap except for actually jumping to
* the handler.
*/
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
{
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
//MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
//MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState();
//Increment the trap level
TL++;
tc->setMiscRegNoEffect(MISCREG_TL, TL);
Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
//Save off state
//set TSTATE.gl to gl
replaceBits(TSTATE, 42, 40, GL);
//set TSTATE.ccr to ccr
replaceBits(TSTATE, 39, 32, CCR);
//set TSTATE.asi to asi
replaceBits(TSTATE, 31, 24, ASI);
//set TSTATE.pstate to pstate
replaceBits(TSTATE, 20, 8, PSTATE);
//set TSTATE.cwp to cwp
replaceBits(TSTATE, 4, 0, CWP);
//Write back TSTATE
tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
//set TPC to PC
tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
//set TNPC to NPC
tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
//set HTSTATE.hpstate to hpstate
tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
//TT = trap type;
tc->setMiscRegNoEffect(MISCREG_TT, tt);
//Update the global register level
if (!gotoHpriv)
tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL));
else
tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
//PSTATE.mm is unchanged
PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
PSTATE &= ~(1 << 3); //PSTATE.am = 0
PSTATE &= ~(1 << 1); //PSTATE.ie = 0
//PSTATE.tle is unchanged
//PSTATE.tct = 0
if (gotoHpriv)
{
PSTATE &= ~(1 << 9); // PSTATE.cle = 0
//The manual says PSTATE.priv should be 0, but Legion leaves it alone
HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
//HPSTATE.tlz is unchanged
tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
} else { // we are going to priv
PSTATE |= (1 << 2); //PSTATE.priv = 1
replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
}
tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
bool changedCWP = true;
if (tt == 0x24)
CWP++;
else if (0x80 <= tt && tt <= 0xbf)
CWP += (CANSAVE + 2);
else if (0xc0 <= tt && tt <= 0xff)
CWP--;
else
changedCWP = false;
if (changedCWP)
{
CWP = (CWP + NWindows) % NWindows;
tc->setMiscReg(MISCREG_CWP, CWP);
}
}
void getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
{
//XXX The following constant might belong in a header file.
const Addr RSTVAddr = 0xFFF0000000ULL;
PC = RSTVAddr | ((TT << 5) & 0xFF);
NPC = PC + sizeof(MachInst);
}
void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
{
Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
NPC = PC + sizeof(MachInst);
}
void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
{
Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
PC = (TBA & ~mask(15)) |
(TL > 1 ? (1 << 14) : 0) |
((TT << 5) & mask(14));
NPC = PC + sizeof(MachInst);
}
#if FULL_SYSTEM
void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
//panic("Invoking a second fault!\n");
FaultBase::invoke(tc);
countStat()++;
//We can refer to this to see what the trap level -was-, but something
//in the middle could change it in the regfile out from under us.
MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
Addr PC, NPC;
PrivilegeLevel current;
if (hpstate & HPSTATE::hpriv)
current = Hyperprivileged;
else if (pstate & PSTATE::priv)
current = Privileged;
else
current = User;
PrivilegeLevel level = getNextLevel(current);
if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
getREDVector(5, PC, NPC);
doREDFault(tc, tt);
//This changes the hpstate and pstate, so we need to make sure we
//save the old version on the trap stack in doREDFault.
enterREDState(tc);
} else if (tl == MaxTL) {
panic("Should go to error state here.. crap\n");
//Do error_state somehow?
//Probably inject a WDR fault using the interrupt mechanism.
//What should the PC and NPC be set to?
} else if (tl > MaxPTL && level == Privileged) {
//guest_watchdog fault
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, 2);
} else if (level == Hyperprivileged ||
(level == Privileged && trapType() >= 384)) {
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, trapType());
} else {
doNormalFault(tc, trapType(), false);
getPrivVector(tc, PC, NPC, trapType(), tl+1);
}
PCState pc;
pc.pc(PC);
pc.npc(NPC);
pc.nnpc(NPC + sizeof(MachInst));
pc.upc(0);
pc.nupc(1);
tc->pcState(pc);
}
void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
{
//For SPARC, when a system is first started, there is a power
//on reset Trap which sets the processor into the following state.
//Bits that aren't set aren't defined on startup.
tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
tc->setMiscRegNoEffect(MISCREG_TT, trapType());
tc->setMiscReg(MISCREG_GL, MaxGL);
//Turn on pef and priv, set everything else to 0
tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
//Turn on red and hpriv, set everything else to 0
MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
//HPSTATE.red = 1
HPSTATE |= (1 << 5);
//HPSTATE.hpriv = 1
HPSTATE |= (1 << 2);
//HPSTATE.ibe = 0
HPSTATE &= ~(1 << 10);
//HPSTATE.tlz = 0
HPSTATE &= ~(1 << 0);
tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
//The tick register is unreadable by nonprivileged software
tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
//Enter RED state. We do this last so that the actual state preserved in
//the trap stack is the state from before this fault.
enterREDState(tc);
Addr PC, NPC;
getREDVector(trapType(), PC, NPC);
PCState pc;
pc.pc(PC);
pc.npc(NPC);
pc.nnpc(NPC + sizeof(MachInst));
pc.upc(0);
pc.nupc(1);
tc->pcState(pc);
//These registers are specified as "undefined" after a POR, and they
//should have reasonable values after the miscregfile is reset
/*
// Clear all the soft interrupt bits
softint = 0;
// disable timer compare interrupts, reset tick_cmpr
tc->setMiscRegNoEffect(MISCREG_
tick_cmprFields.int_dis = 1;
tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
stickFields.npt = 1; //The TICK register is unreadable by by !priv
stick_cmprFields.int_dis = 1; // disable timer compare interrupts
stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
tt[tl] = _trapType;
hintp = 0; // no interrupts pending
hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
*/
}
#else // !FULL_SYSTEM
void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
StaticInstPtr inst)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(vaddr, entry);
if(!success) {
panic("Tried to execute unmapped address %#x.\n", vaddr);
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
p->M5_pid /*context id*/, false, entry.pte);
}
}
void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;
bool success = p->pTable->lookup(vaddr, entry);
if(!success) {
p->checkAndAllocNextPage(vaddr);
success = p->pTable->lookup(vaddr, entry);
}
if(!success) {
panic("Tried to access unmapped address %#x.\n", vaddr);
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
p->M5_pid /*context id*/, false, entry.pte);
}
}
void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
doNormalFault(tc, trapType(), false);
Process *p = tc->getProcessPtr();
//XXX This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
//Then adjust the PC and NPC
tc->pcState(lp->readSpillStart());
}
void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
doNormalFault(tc, trapType(), false);
Process * p = tc->getProcessPtr();
//XXX This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
//Then adjust the PC and NPC
tc->pcState(lp->readFillStart());
}
void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
//In SE, this mechanism is how the process requests a service from the
//operating system. We'll get the process object from the thread context
//and let it service the request.
Process *p = tc->getProcessPtr();
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
lp->handleTrap(_n, tc);
//We need to explicitly advance the pc, since that's not done for us
//on a faulting instruction
PCState pc = tc->pcState();
pc.advance();
tc->pcState(pc);
}
#endif
} // namespace SparcISA
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