98c94cfe3c
The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
278 lines
9 KiB
C++
278 lines
9 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* RubySystem.cc
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*
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* Description: See System.hh
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*
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* $Id$
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*
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*/
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#include "mem/ruby/system/System.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/recorder/Tracer.hh"
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#include "mem/protocol/Protocol.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "mem/ruby/system/DMASequencer.hh"
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#include "mem/ruby/system/MemoryVector.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/system/CacheMemory.hh"
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#include "mem/ruby/system/DirectoryMemory.hh"
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#include "mem/ruby/network/simple/Topology.hh"
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#include "mem/ruby/network/simple/SimpleNetwork.hh"
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#include "mem/ruby/system/RubyPort.hh"
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//#include "mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh"
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//#include "mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh"
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#include "mem/ruby/system/MemoryControl.hh"
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int RubySystem::m_random_seed;
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bool RubySystem::m_randomization;
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int RubySystem::m_tech_nm;
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int RubySystem::m_freq_mhz;
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int RubySystem::m_block_size_bytes;
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int RubySystem::m_block_size_bits;
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uint64 RubySystem::m_memory_size_bytes;
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int RubySystem::m_memory_size_bits;
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map< string, RubyPort* > RubySystem::m_ports;
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map< string, CacheMemory* > RubySystem::m_caches;
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map< string, DirectoryMemory* > RubySystem::m_directories;
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map< string, Sequencer* > RubySystem::m_sequencers;
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map< string, DMASequencer* > RubySystem::m_dma_sequencers;
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map< string, AbstractController* > RubySystem::m_controllers;
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map< string, MemoryControl* > RubySystem::m_memorycontrols;
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Network* RubySystem::m_network_ptr;
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map< string, Topology*> RubySystem::m_topologies;
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Profiler* RubySystem::m_profiler_ptr;
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Tracer* RubySystem::m_tracer_ptr;
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MemoryVector* RubySystem::m_mem_vec_ptr;
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RubySystem::RubySystem(const Params *p)
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: SimObject(p)
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{
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if (g_system_ptr != NULL)
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fatal("Only one RubySystem object currently allowed.\n");
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m_random_seed = p->random_seed;
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srandom(m_random_seed);
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m_randomization = p->randomization;
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m_tech_nm = p->tech_nm;
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m_freq_mhz = p->freq_mhz;
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m_block_size_bytes = p->block_size_bytes;
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assert(is_power_of_2(m_block_size_bytes));
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m_block_size_bits = log_int(m_block_size_bytes);
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m_network_ptr = p->network;
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g_debug_ptr = p->debug;
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m_profiler_ptr = p->profiler;
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m_tracer_ptr = p->tracer;
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g_system_ptr = this;
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m_mem_vec_ptr = new MemoryVector;
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}
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void RubySystem::init()
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{
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// calculate system-wide parameters
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m_memory_size_bytes = 0;
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DirectoryMemory* prev = NULL;
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for (map< string, DirectoryMemory*>::const_iterator it = m_directories.begin();
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it != m_directories.end(); it++) {
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if (prev != NULL)
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assert((*it).second->getSize() == prev->getSize()); // must be equal for proper address mapping
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m_memory_size_bytes += (*it).second->getSize();
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prev = (*it).second;
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}
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m_mem_vec_ptr->setSize(m_memory_size_bytes);
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m_memory_size_bits = log_int(m_memory_size_bytes);
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}
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RubySystem::~RubySystem()
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{
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}
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void RubySystem::printSystemConfig(ostream & out)
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{
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out << "RubySystem config:" << endl;
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out << " random_seed: " << m_random_seed << endl;
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out << " randomization: " << m_randomization << endl;
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out << " tech_nm: " << m_tech_nm << endl;
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out << " freq_mhz: " << m_freq_mhz << endl;
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out << " block_size_bytes: " << m_block_size_bytes << endl;
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out << " block_size_bits: " << m_block_size_bits << endl;
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out << " memory_size_bytes: " << m_memory_size_bytes << endl;
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out << " memory_size_bits: " << m_memory_size_bits << endl;
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}
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void RubySystem::printConfig(ostream& out)
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{
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out << "\n================ Begin RubySystem Configuration Print ================\n\n";
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printSystemConfig(out);
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for (map<string, AbstractController*>::const_iterator it = m_controllers.begin();
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it != m_controllers.end(); it++) {
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(*it).second->printConfig(out);
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}
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for (map<string, CacheMemory*>::const_iterator it = m_caches.begin();
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it != m_caches.end(); it++) {
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(*it).second->printConfig(out);
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}
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DirectoryMemory::printGlobalConfig(out);
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for (map<string, DirectoryMemory*>::const_iterator it = m_directories.begin();
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it != m_directories.end(); it++) {
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(*it).second->printConfig(out);
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}
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for (map<string, Sequencer*>::const_iterator it = m_sequencers.begin();
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it != m_sequencers.end(); it++) {
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(*it).second->printConfig(out);
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}
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m_network_ptr->printConfig(out);
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m_profiler_ptr->printConfig(out);
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out << "\n================ End RubySystem Configuration Print ================\n\n";
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}
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void RubySystem::printStats(ostream& out)
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{
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const time_t T = time(NULL);
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tm *localTime = localtime(&T);
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char buf[100];
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strftime(buf, 100, "%b/%d/%Y %H:%M:%S", localTime);
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out << "Real time: " << buf << endl;
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m_profiler_ptr->printStats(out);
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m_network_ptr->printStats(out);
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for (map<string, Sequencer*>::const_iterator it = m_sequencers.begin();
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it != m_sequencers.end(); it++) {
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(*it).second->printStats(out);
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}
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for (map<string, CacheMemory*>::const_iterator it = m_caches.begin();
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it != m_caches.end(); it++) {
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(*it).second->printStats(out);
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}
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for (map<string, AbstractController*>::const_iterator it = m_controllers.begin();
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it != m_controllers.end(); it++) {
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(*it).second->printStats(out);
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}
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}
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void RubySystem::clearStats() const
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{
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m_profiler_ptr->clearStats();
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m_network_ptr->clearStats();
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for (map<string, CacheMemory*>::const_iterator it = m_caches.begin();
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it != m_caches.end(); it++) {
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(*it).second->clearStats();
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}
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for (map<string, AbstractController*>::const_iterator it = m_controllers.begin();
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it != m_controllers.end(); it++) {
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(*it).second->clearStats();
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}
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}
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void RubySystem::recordCacheContents(CacheRecorder& tr) const
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{
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}
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#ifdef CHECK_COHERENCE
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// This code will check for cases if the given cache block is exclusive in
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// one node and shared in another-- a coherence violation
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//
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// To use, the SLICC specification must call sequencer.checkCoherence(address)
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// when the controller changes to a state with new permissions. Do this
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// in setState. The SLICC spec must also define methods "isBlockShared"
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// and "isBlockExclusive" that are specific to that protocol
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//
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void RubySystem::checkGlobalCoherenceInvariant(const Address& addr ) {
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/*
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NodeID exclusive = -1;
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bool sharedDetected = false;
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NodeID lastShared = -1;
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for (int i = 0; i < m_chip_vector.size(); i++) {
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if (m_chip_vector[i]->isBlockExclusive(addr)) {
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if (exclusive != -1) {
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// coherence violation
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WARN_EXPR(exclusive);
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WARN_EXPR(m_chip_vector[i]->getID());
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WARN_EXPR(addr);
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WARN_EXPR(g_eventQueue_ptr->getTime());
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ERROR_MSG("Coherence Violation Detected -- 2 exclusive chips");
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}
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else if (sharedDetected) {
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WARN_EXPR(lastShared);
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WARN_EXPR(m_chip_vector[i]->getID());
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WARN_EXPR(addr);
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WARN_EXPR(g_eventQueue_ptr->getTime());
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ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
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}
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else {
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exclusive = m_chip_vector[i]->getID();
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}
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}
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else if (m_chip_vector[i]->isBlockShared(addr)) {
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sharedDetected = true;
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lastShared = m_chip_vector[i]->getID();
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if (exclusive != -1) {
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WARN_EXPR(lastShared);
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WARN_EXPR(exclusive);
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WARN_EXPR(addr);
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WARN_EXPR(g_eventQueue_ptr->getTime());
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ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
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}
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}
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}
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*/
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}
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#endif
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RubySystem *
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RubySystemParams::create()
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{
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return new RubySystem(this);
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}
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