66f5124e2b
This class simply cleans up the code by making use of the EventWrapper convenience class to schedule the sendEvent in the bridge ports.
393 lines
12 KiB
C++
393 lines
12 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Steve Reinhardt
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* Andreas Hansson
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*/
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/**
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* @file
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* Declaration of a memory-mapped bus bridge that connects a master
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* and a slave through a request and response queue.
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*/
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#ifndef __MEM_BRIDGE_HH__
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#define __MEM_BRIDGE_HH__
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#include <list>
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#include <queue>
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#include <string>
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#include "base/types.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "params/Bridge.hh"
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#include "sim/eventq.hh"
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/**
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* A bridge is used to interface two different busses (or in general a
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* memory-mapped master and slave), with buffering for requests and
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* responses. The bridge has a fixed delay for packets passing through
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* it and responds to a fixed set of address ranges.
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*
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* The bridge comprises a slave port and a master port, that buffer
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* outgoing responses and requests respectively. Buffer space is
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* reserved when a request arrives, also reserving response space
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* before forwarding the request. An incoming request is always
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* accepted (recvTiming returns true), but is potentially NACKed if
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* there is no request space or response space.
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*/
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class Bridge : public MemObject
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{
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protected:
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/**
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* A bridge request state stores packets along with their sender
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* state and original source. It has enough information to also
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* restore the response once it comes back to the bridge.
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*/
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class RequestState : public Packet::SenderState
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{
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public:
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Packet::SenderState *origSenderState;
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PortID origSrc;
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RequestState(PacketPtr _pkt)
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: origSenderState(_pkt->senderState),
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origSrc(_pkt->getSrc())
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{ }
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void fixResponse(PacketPtr pkt)
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{
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assert(pkt->senderState == this);
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pkt->setDest(origSrc);
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pkt->senderState = origSenderState;
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}
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};
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/**
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* A deferred request stores a packet along with its scheduled
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* transmission time, and whether we can expect to see a response
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* or not.
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*/
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class DeferredRequest
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{
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public:
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Tick ready;
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PacketPtr pkt;
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bool expectResponse;
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DeferredRequest(PacketPtr _pkt, Tick t)
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: ready(t), pkt(_pkt), expectResponse(_pkt->needsResponse())
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{ }
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};
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/**
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* A deferred response stores a packet along with its scheduled
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* transmission time. It also contains information of whether the
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* bridge NACKed the packet to be able to correctly maintain
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* counters of outstanding responses.
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*/
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class DeferredResponse {
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public:
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Tick ready;
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PacketPtr pkt;
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bool nackedHere;
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DeferredResponse(PacketPtr _pkt, Tick t, bool nack = false)
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: ready(t), pkt(_pkt), nackedHere(nack)
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{ }
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};
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// Forward declaration to allow the slave port to have a pointer
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class BridgeMasterPort;
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/**
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* The port on the side that receives requests and sends
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* responses. The slave port has a set of address ranges that it
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* is responsible for. The slave port also has a buffer for the
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* responses not yet sent.
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*/
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class BridgeSlavePort : public SlavePort
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{
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private:
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/** A pointer to the bridge to which this port belongs. */
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Bridge *bridge;
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/**
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* Master port on the other side of the bridge
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* (connected to the other bus).
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*/
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BridgeMasterPort& masterPort;
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/** Minimum request delay though this bridge. */
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Tick delay;
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/** Min delay to respond with a nack. */
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Tick nackDelay;
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/** Address ranges to pass through the bridge */
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AddrRangeList ranges;
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/**
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* Response packet queue. Response packets are held in this
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* queue for a specified delay to model the processing delay
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* of the bridge.
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*/
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std::list<DeferredResponse> responseQueue;
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/** Counter to track the outstanding responses. */
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unsigned int outstandingResponses;
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/** If we're waiting for a retry to happen. */
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bool inRetry;
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/** Max queue size for reserved responses. */
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unsigned int respQueueLimit;
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/**
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* Is this side blocked from accepting new response packets.
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*
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* @return true if the reserved space has reached the set limit
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*/
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bool respQueueFull();
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/**
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* Turn the request packet into a NACK response and put it in
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* the response queue and schedule its transmission.
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*
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* @param pkt the request packet to NACK
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*/
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void nackRequest(PacketPtr pkt);
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/**
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* Handle send event, scheduled when the packet at the head of
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* the response queue is ready to transmit (for timing
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* accesses only).
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*/
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void trySend();
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/** Send event for the response queue. */
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EventWrapper<BridgeSlavePort, &BridgeSlavePort::trySend> sendEvent;
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public:
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/**
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* Constructor for the BridgeSlavePort.
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*
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* @param _name the port name including the owner
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* @param _bridge the structural owner
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* @param _masterPort the master port on the other side of the bridge
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* @param _delay the delay from seeing a response to sending it
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* @param _nack_delay the delay from a NACK to sending the response
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* @param _resp_limit the size of the response queue
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* @param _ranges a number of address ranges to forward
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*/
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BridgeSlavePort(const std::string &_name, Bridge *_bridge,
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BridgeMasterPort& _masterPort, int _delay,
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int _nack_delay, int _resp_limit,
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std::vector<Range<Addr> > _ranges);
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/**
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* Queue a response packet to be sent out later and also schedule
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* a send if necessary.
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*
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* @param pkt a response to send out after a delay
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*/
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void queueForSendTiming(PacketPtr pkt);
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protected:
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/** When receiving a timing request from the peer port,
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pass it to the bridge. */
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virtual bool recvTimingReq(PacketPtr pkt);
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/** When receiving a retry request from the peer port,
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pass it to the bridge. */
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virtual void recvRetry();
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/** When receiving a Atomic requestfrom the peer port,
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pass it to the bridge. */
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virtual Tick recvAtomic(PacketPtr pkt);
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/** When receiving a Functional request from the peer port,
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pass it to the bridge. */
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virtual void recvFunctional(PacketPtr pkt);
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/** When receiving a address range request the peer port,
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pass it to the bridge. */
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virtual AddrRangeList getAddrRanges() const;
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};
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/**
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* Port on the side that forwards requests and receives
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* responses. The master port has a buffer for the requests not
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* yet sent.
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*/
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class BridgeMasterPort : public MasterPort
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{
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private:
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/** A pointer to the bridge to which this port belongs. */
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Bridge* bridge;
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/**
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* Pointer to the slave port on the other side of the bridge
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* (connected to the other bus).
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*/
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BridgeSlavePort& slavePort;
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/** Minimum delay though this bridge. */
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Tick delay;
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/**
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* Request packet queue. Request packets are held in this
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* queue for a specified delay to model the processing delay
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* of the bridge.
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*/
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std::list<DeferredRequest> requestQueue;
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/** If we're waiting for a retry to happen. */
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bool inRetry;
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/** Max queue size for request packets */
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unsigned int reqQueueLimit;
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/**
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* Handle send event, scheduled when the packet at the head of
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* the outbound queue is ready to transmit (for timing
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* accesses only).
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*/
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void trySend();
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/** Send event for the request queue. */
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EventWrapper<BridgeMasterPort, &BridgeMasterPort::trySend> sendEvent;
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public:
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/**
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* Constructor for the BridgeMasterPort.
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*
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* @param _name the port name including the owner
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* @param _bridge the structural owner
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* @param _slavePort the slave port on the other side of the bridge
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* @param _delay the delay from seeing a request to sending it
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* @param _req_limit the size of the request queue
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*/
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BridgeMasterPort(const std::string &_name, Bridge *_bridge,
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BridgeSlavePort& _slavePort, int _delay,
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int _req_limit);
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/**
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* Is this side blocked from accepting new request packets.
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*
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* @return true if the occupied space has reached the set limit
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*/
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bool reqQueueFull();
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/**
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* Queue a request packet to be sent out later and also schedule
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* a send if necessary.
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*
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* @param pkt a request to send out after a delay
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*/
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void queueForSendTiming(PacketPtr pkt);
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/**
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* Check a functional request against the packets in our
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* request queue.
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*
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* @param pkt packet to check against
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*
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* @return true if we find a match
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*/
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bool checkFunctional(PacketPtr pkt);
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protected:
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/** When receiving a timing request from the peer port,
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pass it to the bridge. */
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virtual bool recvTimingResp(PacketPtr pkt);
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/** When receiving a retry request from the peer port,
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pass it to the bridge. */
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virtual void recvRetry();
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};
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/** Slave port of the bridge. */
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BridgeSlavePort slavePort;
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/** Master port of the bridge. */
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BridgeMasterPort masterPort;
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/** If this bridge should acknowledge writes. */
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bool ackWrites;
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public:
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typedef BridgeParams Params;
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protected:
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Params *_params;
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public:
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const Params *params() const { return _params; }
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virtual MasterPort& getMasterPort(const std::string& if_name,
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int idx = -1);
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virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
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virtual void init();
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Bridge(Params *p);
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};
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#endif //__MEM_BUS_HH__
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