cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
604 lines
69 KiB
Text
604 lines
69 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.139855 # Number of seconds simulated
|
|
sim_ticks 139855372500 # Number of ticks simulated
|
|
final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 118034 # Simulator instruction rate (inst/s)
|
|
host_op_rate 118034 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 41407532 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 230404 # Number of bytes of host memory used
|
|
host_seconds 3377.53 # Real time elapsed on the host
|
|
sim_insts 398664595 # Number of instructions simulated
|
|
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory
|
|
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 7328 # Total number of read requests seen
|
|
system.physmem.writeReqs 0 # Total number of write requests seen
|
|
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
|
|
system.physmem.bytesRead 468992 # Total number of bytes read from memory
|
|
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
|
system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
|
|
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
|
|
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
|
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
|
system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis
|
|
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
|
system.physmem.totGap 139855320500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::6 7328 # Categorize read packet sizes
|
|
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
|
system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
system.physmem.totQLat 47654000 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 36640000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 113038750 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 6503.00 # Average queueing delay per request
|
|
system.physmem.avgBankLat 15425.59 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 26928.60 # Average memory access latency
|
|
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
|
system.physmem.readRowHits 6132 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
|
system.physmem.avgGap 19085060.11 # Average gap between requests
|
|
system.cpu.branchPred.lookups 53489671 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 94754610 # DTB read hits
|
|
system.cpu.dtb.read_misses 21 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 94754631 # DTB read accesses
|
|
system.cpu.dtb.write_hits 73521101 # DTB write hits
|
|
system.cpu.dtb.write_misses 35 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 73521136 # DTB write accesses
|
|
system.cpu.dtb.data_hits 168275711 # DTB hits
|
|
system.cpu.dtb.data_misses 56 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 168275767 # DTB accesses
|
|
system.cpu.itb.fetch_hits 48611339 # ITB hits
|
|
system.cpu.itb.fetch_misses 44520 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 48655859 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 215 # Number of system calls
|
|
system.cpu.numCycles 279710746 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True).
|
|
system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False).
|
|
system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File
|
|
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
|
system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File
|
|
system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File
|
|
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
|
system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File
|
|
system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic
|
|
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
|
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts
|
|
system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed.
|
|
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
|
system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 95.207865 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
|
system.cpu.comStores 73520729 # Number of Store instructions committed
|
|
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
|
system.cpu.comNops 23089775 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 112239074 # Number of Integer instructions committed
|
|
system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 172651735 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 180966170 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 35.302389 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 90242832 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 189467914 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 67.737088 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 1975 # number of replacements
|
|
system.cpu.icache.tagsinuse 1831.214739 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 48606831 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 12453.710223 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.894148 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.894148 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 48606831 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 48606831 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 48606831 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 48606831 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 48606831 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 48606831 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 4508 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 205410000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 205410000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 205410000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 205410000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 205410000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 205410000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 48611339 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 48611339 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 48611339 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 48611339 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 48611339 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 48611339 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 45565.661047 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 45565.661047 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 68.666667 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 605 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 605 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 605 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 605 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 605 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 605 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179905000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 179905000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179905000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 179905000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179905000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 179905000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46094.030233 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46094.030233 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2909.305713 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 627.697804 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.088785 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.119252 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 544 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 727 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 544 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 727 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3359 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3359 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 170516000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45771500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 216287500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 159323000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 159323000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 170516000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 205094500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 375610500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 170516000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 205094500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 375610500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 3903 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8055 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 3903 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8055 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.860620 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.862474 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.860620 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.909745 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50763.917833 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55547.936893 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51706.311260 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50659.141494 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50659.141494 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51256.891376 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51256.891376 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3359 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3359 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128894552 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549355 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164443907 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120757665 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120757665 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128894552 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156307020 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 285201572 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128894552 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156307020 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 285201572 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38372.894314 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43142.421117 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39312.432943 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38396.713831 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38396.713831 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 764 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 168254397 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 40523.698699 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3285.521075 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.802129 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.802129 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 94753186 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 94753186 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73501211 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 73501211 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 168254397 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 168254397 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 168254397 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 168254397 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1303 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1303 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 19518 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 19518 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 20821 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 20821 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 20821 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 20821 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65740000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 65740000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 753340000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 753340000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 819080000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 819080000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 819080000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 819080000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50452.801228 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 50452.801228 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38597.192335 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38597.192335 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 39339.128764 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 39339.128764 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 18390 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 537 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.245810 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 353 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 353 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16316 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 16316 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 16669 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 16669 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 16669 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 16669 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48200500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163094000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 163094000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211294500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|