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base_dyn_inst.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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bpred_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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bpred_unit.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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bpred_unit_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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checker_builder.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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comm.hh
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O3: Cleanup the commitInfo comm struct.
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2011-03-17 19:20:19 -05:00 |
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commit.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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commit.hh
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includes: fix up code after sorting
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2011-04-15 10:44:14 -07:00 |
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commit_impl.hh
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stats: rename stats so they can be used as python expressions
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2011-04-19 18:45:21 -07:00 |
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cpu.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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cpu.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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cpu_builder.cc
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o3-smt: enforce numThreads parameter for SMT SE mode
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2009-07-25 00:50:27 -04:00 |
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cpu_policy.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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decode.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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decode.hh
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Move sched_list.hh and timebuf.hh from src/base to src/cpu.
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2011-01-03 14:35:47 -08:00 |
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decode_impl.hh
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stats: rename stats so they can be used as python expressions
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2011-04-19 18:45:21 -07:00 |
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dep_graph.hh
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ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
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2010-10-31 00:07:20 -07:00 |
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dyn_inst.cc
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O3: Generaize the O3 IMPL class so it isn't split out by ISA.
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2008-10-09 00:10:02 -07:00 |
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dyn_inst.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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dyn_inst_impl.hh
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O3: Make all instructions that write a misc. register not perform the write until commit.
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2010-12-07 16:19:57 -08:00 |
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fetch.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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fetch.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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fetch_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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free_list.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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free_list.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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fu_pool.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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fu_pool.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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FuncUnitConfig.py
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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FUPool.py
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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iew.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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iew.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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iew_impl.hh
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stats: rename stats so they can be used as python expressions
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2011-04-19 18:45:21 -07:00 |
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impl.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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inst_queue.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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inst_queue.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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inst_queue_impl.hh
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stats: rename stats so they can be used as python expressions
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2011-04-19 18:45:21 -07:00 |
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isa_specific.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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lsq.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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lsq.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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lsq_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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lsq_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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lsq_unit.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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lsq_unit_impl.hh
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O3: Fix a small corner case with the lsq hazard detection logic.
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2011-05-04 20:38:26 -05:00 |
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mem_dep_unit.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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mem_dep_unit.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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mem_dep_unit_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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O3Checker.py
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python: Move more code into m5.util allow SCons to use that code.
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2009-09-22 15:24:16 -07:00 |
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O3CPU.py
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O3: Tighten memory order violation checking to 16 bytes.
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2011-04-04 11:42:23 -05:00 |
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regfile.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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rename.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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rename.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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rename_impl.hh
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stats: rename stats so they can be used as python expressions
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2011-04-19 18:45:21 -07:00 |
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rename_map.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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rename_map.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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rob.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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rob.hh
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includes: fix up code after sorting
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2011-04-15 10:44:14 -07:00 |
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rob_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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sat_counter.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
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sat_counter.hh
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types: Move stuff for global types into src/base/types.hh
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2009-05-17 14:34:50 -07:00 |
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SConscript
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inorder-o3: allow both to compile together
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2009-05-12 15:01:14 -04:00 |
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SConsopts
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cpu_models: get rid of cpu_models.py and move the stuff into SCons
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2010-02-26 18:14:48 -08:00 |
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scoreboard.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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scoreboard.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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store_set.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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store_set.hh
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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thread_context.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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thread_context.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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thread_context_impl.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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thread_state.hh
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Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
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2009-07-08 23:02:22 -07:00 |
