418 lines
13 KiB
C++
418 lines
13 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_THREAD_CONTEXT_HH__
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#define __CPU_THREAD_CONTEXT_HH__
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#include <iostream>
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#include <string>
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#include "arch/registers.hh"
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#include "arch/types.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// DTB pointers.
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namespace TheISA
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{
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class TLB;
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}
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class BaseCPU;
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class Checkpoint;
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class EndQuiesceEvent;
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class TranslatingPort;
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class FunctionalPort;
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class VirtualPort;
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class Process;
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class System;
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namespace TheISA {
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namespace Kernel {
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class Statistics;
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};
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};
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/**
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* ThreadContext is the external interface to all thread state for
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* anything outside of the CPU. It provides all accessor methods to
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* state that might be needed by external objects, ranging from
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* register values to things such as kernel stats. It is an abstract
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* base class; the CPU can create its own ThreadContext by either
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* deriving from it, or using the templated ProxyThreadContext.
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*
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* The ThreadContext is slightly different than the ExecContext. The
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* ThreadContext provides access to an individual thread's state; an
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* ExecContext provides ISA access to the CPU (meaning it is
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* implicitly multithreaded on SMT systems). Additionally the
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* ThreadState is an abstract class that exactly defines the
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* interface; the ExecContext is a more implicit interface that must
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* be implemented so that the ISA can access whatever state it needs.
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*/
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class ThreadContext
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscReg MiscReg;
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public:
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enum Status
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{
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/// Running. Instructions should be executed only when
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/// the context is in this state.
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Active,
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/// Temporarily inactive. Entered while waiting for
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/// synchronization, etc.
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Suspended,
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/// Permanently shut down. Entered when target executes
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/// m5exit pseudo-instruction. When all contexts enter
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/// this state, the simulation will terminate.
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Halted
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};
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virtual ~ThreadContext() { };
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virtual BaseCPU *getCpuPtr() = 0;
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virtual int cpuId() = 0;
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virtual int threadId() = 0;
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virtual void setThreadId(int id) = 0;
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virtual int contextId() = 0;
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virtual void setContextId(int id) = 0;
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virtual TheISA::TLB *getITBPtr() = 0;
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virtual TheISA::TLB *getDTBPtr() = 0;
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virtual System *getSystemPtr() = 0;
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#if FULL_SYSTEM
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virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
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virtual FunctionalPort *getPhysPort() = 0;
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virtual VirtualPort *getVirtPort() = 0;
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virtual void connectMemPorts(ThreadContext *tc) = 0;
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#else
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virtual TranslatingPort *getMemPort() = 0;
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virtual Process *getProcessPtr() = 0;
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#endif
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virtual Status status() const = 0;
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virtual void setStatus(Status new_status) = 0;
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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virtual void activate(int delay = 1) = 0;
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/// Set the status to Suspended.
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virtual void suspend(int delay = 0) = 0;
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/// Set the status to Halted.
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virtual void halt(int delay = 0) = 0;
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#if FULL_SYSTEM
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virtual void dumpFuncProfile() = 0;
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#endif
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virtual void takeOverFrom(ThreadContext *old_context) = 0;
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virtual void regStats(const std::string &name) = 0;
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virtual void serialize(std::ostream &os) = 0;
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virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
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#if FULL_SYSTEM
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virtual EndQuiesceEvent *getQuiesceEvent() = 0;
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// Not necessarily the best location for these...
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// Having an extra function just to read these is obnoxious
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virtual Tick readLastActivate() = 0;
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virtual Tick readLastSuspend() = 0;
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virtual void profileClear() = 0;
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virtual void profileSample() = 0;
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#endif
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virtual void copyArchRegs(ThreadContext *tc) = 0;
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virtual void clearArchRegs() = 0;
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//
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// New accessors for new decoder.
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//
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virtual uint64_t readIntReg(int reg_idx) = 0;
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virtual FloatReg readFloatReg(int reg_idx) = 0;
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virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
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virtual void setIntReg(int reg_idx, uint64_t val) = 0;
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virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
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virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
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virtual TheISA::PCState pcState() = 0;
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virtual void pcState(const TheISA::PCState &val) = 0;
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virtual Addr instAddr() = 0;
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virtual Addr nextInstAddr() = 0;
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virtual MicroPC microPC() = 0;
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virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
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virtual MiscReg readMiscReg(int misc_reg) = 0;
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virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
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virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
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virtual int flattenIntIndex(int reg) = 0;
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virtual int flattenFloatIndex(int reg) = 0;
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virtual uint64_t
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readRegOtherThread(int misc_reg, ThreadID tid)
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{
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return 0;
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}
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virtual void
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setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
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{
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}
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// Also not necessarily the best location for these two. Hopefully will go
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// away once we decide upon where st cond failures goes.
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virtual unsigned readStCondFailures() = 0;
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virtual void setStCondFailures(unsigned sc_failures) = 0;
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// Only really makes sense for old CPU model. Still could be useful though.
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virtual bool misspeculating() = 0;
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#if !FULL_SYSTEM
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// Same with st cond failures.
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virtual Counter readFuncExeInst() = 0;
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virtual void syscall(int64_t callnum) = 0;
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// This function exits the thread context in the CPU and returns
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// 1 if the CPU has no more active threads (meaning it's OK to exit);
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// Used in syscall-emulation mode when a thread calls the exit syscall.
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virtual int exit() { return 1; };
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#endif
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/** function to compare two thread contexts (for debugging) */
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static void compare(ThreadContext *one, ThreadContext *two);
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};
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/**
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* ProxyThreadContext class that provides a way to implement a
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* ThreadContext without having to derive from it. ThreadContext is an
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* abstract class, so anything that derives from it and uses its
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* interface will pay the overhead of virtual function calls. This
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* class is created to enable a user-defined Thread object to be used
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* wherever ThreadContexts are used, without paying the overhead of
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* virtual function calls when it is used by itself. See
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* simple_thread.hh for an example of this.
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*/
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template <class TC>
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class ProxyThreadContext : public ThreadContext
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{
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public:
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ProxyThreadContext(TC *actual_tc)
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{ actualTC = actual_tc; }
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private:
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TC *actualTC;
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public:
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BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
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int cpuId() { return actualTC->cpuId(); }
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int threadId() { return actualTC->threadId(); }
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void setThreadId(int id) { return actualTC->setThreadId(id); }
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int contextId() { return actualTC->contextId(); }
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void setContextId(int id) { actualTC->setContextId(id); }
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TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
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TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
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System *getSystemPtr() { return actualTC->getSystemPtr(); }
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#if FULL_SYSTEM
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TheISA::Kernel::Statistics *getKernelStats()
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{ return actualTC->getKernelStats(); }
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FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
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VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
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void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
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#else
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TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
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Process *getProcessPtr() { return actualTC->getProcessPtr(); }
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#endif
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Status status() const { return actualTC->status(); }
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void setStatus(Status new_status) { actualTC->setStatus(new_status); }
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1) { actualTC->activate(delay); }
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/// Set the status to Suspended.
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void suspend(int delay = 0) { actualTC->suspend(); }
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/// Set the status to Halted.
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void halt(int delay = 0) { actualTC->halt(); }
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#if FULL_SYSTEM
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void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
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#endif
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void takeOverFrom(ThreadContext *oldContext)
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{ actualTC->takeOverFrom(oldContext); }
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void regStats(const std::string &name) { actualTC->regStats(name); }
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void serialize(std::ostream &os) { actualTC->serialize(os); }
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void unserialize(Checkpoint *cp, const std::string §ion)
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{ actualTC->unserialize(cp, section); }
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#if FULL_SYSTEM
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EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
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Tick readLastActivate() { return actualTC->readLastActivate(); }
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Tick readLastSuspend() { return actualTC->readLastSuspend(); }
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void profileClear() { return actualTC->profileClear(); }
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void profileSample() { return actualTC->profileSample(); }
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#endif
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// @todo: Do I need this?
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void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
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void clearArchRegs() { actualTC->clearArchRegs(); }
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{ return actualTC->readIntReg(reg_idx); }
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FloatReg readFloatReg(int reg_idx)
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{ return actualTC->readFloatReg(reg_idx); }
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FloatRegBits readFloatRegBits(int reg_idx)
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{ return actualTC->readFloatRegBits(reg_idx); }
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void setIntReg(int reg_idx, uint64_t val)
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{ actualTC->setIntReg(reg_idx, val); }
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void setFloatReg(int reg_idx, FloatReg val)
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{ actualTC->setFloatReg(reg_idx, val); }
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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{ actualTC->setFloatRegBits(reg_idx, val); }
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TheISA::PCState pcState() { return actualTC->pcState(); }
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void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
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Addr instAddr() { return actualTC->instAddr(); }
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Addr nextInstAddr() { return actualTC->nextInstAddr(); }
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MicroPC microPC() { return actualTC->microPC(); }
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bool readPredicate() { return actualTC->readPredicate(); }
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void setPredicate(bool val)
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{ actualTC->setPredicate(val); }
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MiscReg readMiscRegNoEffect(int misc_reg)
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{ return actualTC->readMiscRegNoEffect(misc_reg); }
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MiscReg readMiscReg(int misc_reg)
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{ return actualTC->readMiscReg(misc_reg); }
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{ return actualTC->setMiscRegNoEffect(misc_reg, val); }
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void setMiscReg(int misc_reg, const MiscReg &val)
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{ return actualTC->setMiscReg(misc_reg, val); }
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int flattenIntIndex(int reg)
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{ return actualTC->flattenIntIndex(reg); }
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int flattenFloatIndex(int reg)
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{ return actualTC->flattenFloatIndex(reg); }
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unsigned readStCondFailures()
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{ return actualTC->readStCondFailures(); }
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void setStCondFailures(unsigned sc_failures)
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{ actualTC->setStCondFailures(sc_failures); }
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// @todo: Fix this!
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bool misspeculating() { return actualTC->misspeculating(); }
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#if !FULL_SYSTEM
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void syscall(int64_t callnum)
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{ actualTC->syscall(callnum); }
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Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
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#endif
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};
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#endif
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