This patch makes the internal links within the network topology unidirectional, thus allowing any deadlock-free routing algorithms to be specified from the topology itself using weights. This patch also renames Mesh.py and MeshDirCorners.py to Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing). It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.
80 lines
3.8 KiB
Python
80 lines
3.8 KiB
Python
# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Brad Beckmann
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from m5.params import *
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from m5.proxy import *
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from Network import RubyNetwork
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from BasicRouter import BasicRouter
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from MessageBuffer import MessageBuffer
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class SimpleNetwork(RubyNetwork):
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type = 'SimpleNetwork'
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cxx_header = "mem/ruby/network/simple/SimpleNetwork.hh"
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buffer_size = Param.Int(0,
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"default buffer size; 0 indicates infinite buffering");
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endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor");
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adaptive_routing = Param.Bool(False, "enable adaptive routing");
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int_link_buffers = VectorParam.MessageBuffer("Buffers for int_links")
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def setup_buffers(self):
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# Note that all SimpleNetwork MessageBuffers are currently ordered
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network_buffers = []
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for link in self.int_links:
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# The network needs number_of_virtual_networks buffers per
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# int_link port
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for i in xrange(self.number_of_virtual_networks):
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network_buffers.append(MessageBuffer(ordered = True))
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network_buffers.append(MessageBuffer(ordered = True))
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self.int_link_buffers = network_buffers
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# Also add buffers for all router-link connections
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for router in self.routers:
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router_buffers = []
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# Add message buffers to routers at the end of each
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# unidirectional internal link
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for link in self.int_links:
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if link.dst_node == router:
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for i in xrange(self.number_of_virtual_networks):
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router_buffers.append(MessageBuffer(ordered = True))
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# Add message buffers to routers for each external link connection
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for link in self.ext_links:
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# Routers can only be int_nodes on ext_links
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if link.int_node in self.routers:
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for i in xrange(self.number_of_virtual_networks):
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router_buffers.append(MessageBuffer(ordered = True))
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router.port_buffers = router_buffers
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class Switch(BasicRouter):
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type = 'Switch'
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cxx_header = 'mem/ruby/network/simple/Switch.hh'
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virt_nets = Param.Int(Parent.number_of_virtual_networks,
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"number of virtual networks")
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port_buffers = VectorParam.MessageBuffer("Port buffers")
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