0d00cbc97b
This patch changes the router pipeline stages from 4 to 2. The canonical 4-stage router is conservative while a lower-latency router with look ahead routing and speculative allocation is well acknowledged.
123 lines
4.3 KiB
C++
123 lines
4.3 KiB
C++
/*
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* Copyright (c) 2008 Princeton University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Niket Agarwal
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*/
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#include "base/stl_helpers.hh"
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#include "mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh"
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#include "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh"
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using namespace std;
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using m5::stl_helpers::deletePointers;
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InputUnit_d::InputUnit_d(int id, Router_d *router) : Consumer(router)
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{
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m_id = id;
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m_router = router;
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m_num_vcs = m_router->get_num_vcs();
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m_vc_per_vnet = m_router->get_vc_per_vnet();
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m_num_buffer_reads.resize(m_num_vcs/m_vc_per_vnet);
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m_num_buffer_writes.resize(m_num_vcs/m_vc_per_vnet);
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for (int i = 0; i < m_num_buffer_reads.size(); i++) {
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m_num_buffer_reads[i] = 0;
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m_num_buffer_writes[i] = 0;
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}
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creditQueue = new flitBuffer_d();
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// Instantiating the virtual channels
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m_vcs.resize(m_num_vcs);
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for (int i=0; i < m_num_vcs; i++) {
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m_vcs[i] = new VirtualChannel_d(i);
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}
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}
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InputUnit_d::~InputUnit_d()
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{
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delete creditQueue;
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deletePointers(m_vcs);
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}
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void
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InputUnit_d::wakeup()
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{
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flit_d *t_flit;
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if (m_in_link->isReady(m_router->curCycle())) {
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t_flit = m_in_link->consumeLink();
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int vc = t_flit->get_vc();
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if ((t_flit->get_type() == HEAD_) ||
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(t_flit->get_type() == HEAD_TAIL_)) {
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assert(m_vcs[vc]->get_state() == IDLE_);
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// Do the route computation for this vc
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m_router->route_req(t_flit, this, vc);
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m_vcs[vc]->set_enqueue_time(m_router->curCycle());
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} else {
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t_flit->advance_stage(SA_, m_router->curCycle());
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// Changing router latency to 2 cycles. Input Unit takes 1 cycle for wakeup.
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// VCalloc, SWalloc, Sw-Xfer and output scheduling takes 1 cycle. The original
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// design schedules VCallocator for head flit, and Swalloc for non-head flit.
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// VCalloc now calls SWalloc directly instead of scheduling it for the next cycle,
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// hence we should not allocate SWalloc, otherwise it might get called twice, once
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// by the scheduler and once by VCalloc.
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m_router->vcarb_req();
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}
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// write flit into input buffer
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m_vcs[vc]->insertFlit(t_flit);
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int vnet = vc/m_vc_per_vnet;
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// number of writes same as reads
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// any flit that is written will be read only once
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m_num_buffer_writes[vnet]++;
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m_num_buffer_reads[vnet]++;
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}
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}
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uint32_t
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InputUnit_d::functionalWrite(Packet *pkt)
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{
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uint32_t num_functional_writes = 0;
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for (int i=0; i < m_num_vcs; i++) {
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num_functional_writes += m_vcs[i]->functionalWrite(pkt);
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}
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return num_functional_writes;
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}
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void
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InputUnit_d::resetStats()
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{
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for (int j = 0; j < m_num_buffer_reads.size(); j++) {
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m_num_buffer_reads[j] = 0;
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m_num_buffer_writes[j] = 0;
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}
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}
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