0fcb376e5f
This patch changes the name of a bunch of packet flags and MSHR member functions and variables to make the coherency protocol easier to understand. In addition the patch adds and updates lots of descriptions, explicitly spelling out assumptions. The following name changes are made: * the packet memInhibit flag is renamed to cacheResponding * the packet sharedAsserted flag is renamed to hasSharers * the packet NeedsExclusive attribute is renamed to NeedsWritable * the packet isSupplyExclusive is renamed responderHadWritable * the MSHR pendingDirty is renamed to pendingModified The cache states, Modified, Owned, Exclusive, Shared are also called out in the cache and MSHR code to make it easier to understand.
118 lines
3.6 KiB
C++
118 lines
3.6 KiB
C++
#include "base/random.hh"
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#include "debug/HMCController.hh"
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#include "mem/hmc_controller.hh"
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HMCController::HMCController(const HMCControllerParams* p) :
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NoncoherentXBar(p),
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n_master_ports(p->port_master_connection_count),
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rr_counter(0)
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{
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assert(p->port_slave_connection_count == 1);
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}
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HMCController*
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HMCControllerParams::create()
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{
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return new HMCController(this);
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}
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// Since this module is a load distributor, all its master ports have the same
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// range so we should keep only one of the ranges and ignore the others
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void HMCController::recvRangeChange(PortID master_port_id)
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{
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if (master_port_id == 0)
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{
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gotAllAddrRanges = true;
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BaseXBar::recvRangeChange(master_port_id);
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}
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else
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gotAddrRanges[master_port_id] = true;
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}
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int HMCController::rotate_counter()
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{
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int current_value = rr_counter;
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rr_counter++;
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if (rr_counter == n_master_ports)
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rr_counter = 0;
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return current_value;
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}
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bool HMCController::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
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{
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// determine the source port based on the id
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SlavePort *src_port = slavePorts[slave_port_id];
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// we should never see express snoops on a non-coherent component
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assert(!pkt->isExpressSnoop());
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// For now, this is a simple round robin counter, for distribution the
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// load among the serial links
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PortID master_port_id = rotate_counter();
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// test if the layer should be considered occupied for the current
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// port
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if (!reqLayers[master_port_id]->tryTiming(src_port)) {
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DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x BUSY\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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return false;
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}
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DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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// store size and command as they might be modified when
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// forwarding the packet
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unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
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unsigned int pkt_cmd = pkt->cmdToIndex();
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// store the old header delay so we can restore it if needed
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Tick old_header_delay = pkt->headerDelay;
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// a request sees the frontend and forward latency
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Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
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// set the packet header and payload delay
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calcPacketTiming(pkt, xbar_delay);
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// determine how long to be layer is busy
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Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
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// before forwarding the packet (and possibly altering it),
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// remember if we are expecting a response
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const bool expect_response = pkt->needsResponse() &&
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!pkt->cacheResponding();
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// since it is a normal request, attempt to send the packet
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bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
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if (!success) {
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DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x RETRY\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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// restore the header delay as it is additive
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pkt->headerDelay = old_header_delay;
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// occupy until the header is sent
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reqLayers[master_port_id]->failedTiming(src_port,
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clockEdge(Cycles(1)));
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return false;
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}
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// remember where to route the response to
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if (expect_response) {
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assert(routeTo.find(pkt->req) == routeTo.end());
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routeTo[pkt->req] = slave_port_id;
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}
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reqLayers[master_port_id]->succeededTiming(packetFinishTime);
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// stats updates
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pktCount[slave_port_id][master_port_id]++;
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pktSize[slave_port_id][master_port_id] += pkt_size;
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transDist[pkt_cmd]++;
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return true;
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}
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