c1aecc05e6
This patch extensively modifies DSENT so that it can be accessed using Python. To access the Python interface, DSENT needs to compiled as a shared library. For this purpose a CMakeLists.txt file has been added. Some of the code that is not required is being removed.
399 lines
19 KiB
C++
399 lines
19 KiB
C++
/* Copyright (c) 2012 Massachusetts Institute of Technology
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "model/electrical/DemuxTreeDeserializer.h"
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#include <cmath>
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#include "model/PortInfo.h"
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#include "model/TransitionInfo.h"
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#include "model/EventInfo.h"
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#include "model/std_cells/StdCellLib.h"
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#include "model/std_cells/StdCell.h"
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#include "model/electrical/Multiplexer.h"
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#include "model/timing_graph/ElectricalNet.h"
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namespace DSENT
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{
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using std::ceil;
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DemuxTreeDeserializer::DemuxTreeDeserializer(const String& instance_name_, const TechModel* tech_model_)
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: ElectricalModel(instance_name_, tech_model_)
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{
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initParameters();
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initProperties();
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}
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DemuxTreeDeserializer::~DemuxTreeDeserializer()
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{}
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void DemuxTreeDeserializer::initParameters()
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{
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addParameterName("InDataRate");
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addParameterName("OutDataRate");
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addParameterName("OutBits"); //Output width will just be output width / serialization ratio
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addParameterName("BitDuplicate", "TRUE");
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return;
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}
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void DemuxTreeDeserializer::initProperties()
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{
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return;
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}
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DemuxTreeDeserializer* DemuxTreeDeserializer::clone() const
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{
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// TODO
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return NULL;
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}
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void DemuxTreeDeserializer::constructModel()
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{
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// Get parameters
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double in_data_rate = getParameter("InDataRate");
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double out_data_rate = getParameter("OutDataRate");
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unsigned int out_bits = getParameter("OutBits");
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bool bit_duplicate = getParameter("BitDuplicate");
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// Calculate deserialization ratio
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unsigned int deserialization_ratio = (unsigned int) floor(in_data_rate / out_data_rate);
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ASSERT(deserialization_ratio == in_data_rate / out_data_rate,
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"[Error] " + getInstanceName() + " -> Cannot have non-integer deserialization ratios!");
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ASSERT((deserialization_ratio & (deserialization_ratio - 1)) == 0,
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"[Error] " + getInstanceName() + " -> Deserialization ratio must be a power of 2");
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// Calculate output width
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unsigned int input_bits = out_bits / deserialization_ratio;
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ASSERT(out_bits >= deserialization_ratio, "[Error] " + getInstanceName() +
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" -> Output width must be >= deserialization ratio!");
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ASSERT(floor((double) out_bits / deserialization_ratio) == input_bits,
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"[Error] " + getInstanceName() + " -> Output width must be a multiple of the serialization ratio!");
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// Store calculated numbers
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getGenProperties()->set("DeserializationRatio", deserialization_ratio);
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getGenProperties()->set("InputBits", input_bits);
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// Create ports
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createInputPort("In", makeNetIndex(0, input_bits-1));
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createInputPort("InCK");
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createOutputPort("Out", makeNetIndex(0, out_bits-1));
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//Create energy, power, and area results
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createElectricalResults();
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createElectricalEventResult("Deserialize");
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getEventInfo("Deserialize")->setTransitionInfo("InCK", TransitionInfo(0.0, (double) deserialization_ratio / 2.0, 0.0));
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// Set conditions during idle state
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getEventInfo("Idle")->setStaticTransitionInfos();
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getEventInfo("Idle")->setTransitionInfo("InCK", TransitionInfo(0.0, (double) deserialization_ratio / 2.0, 0.0));
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// Mark InCK as a false path (since timing tool will do strange stuff due to all the clock divides and stuff)
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getNet("InCK")->setFalsePath(true);
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// Create deserializer
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if (deserialization_ratio == 1)
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{
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// No need to do anything, hohoho
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assign("Out", "In");
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}
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else if (input_bits == 1)
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{
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//-----------------------------------------------------------------
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// Create 2:1 demux deserializer
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//-----------------------------------------------------------------
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const String& des_dff_way0_name = "DesDFFWay0";
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const String& des_dff_way1_name = "DesDFFWay1";
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const String& des_latch_name = "DesLatch";
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const String& ck_dff_name = "CKDFF";
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const String& ck_inv_name = "CKINV";
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const String& out_way0_name = "OutWay0";
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const String& out_way1_name = "OutWay1";
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const String& mid_way0_name = "MidWay0";
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const String& ck_div2_name = "CK_div2";
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const String& ck_div2_b_name = "CK_div2_b";
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// Create nets
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createNet(out_way0_name);
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createNet(out_way1_name);
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createNet(mid_way0_name);
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createNet(ck_div2_name);
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createNet(ck_div2_b_name);
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// Create the dffs and latch needed on both ways
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StdCell* des_dff_way0 = getTechModel()->getStdCellLib()->createStdCell("DFFQ", des_dff_way0_name);
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des_dff_way0->construct();
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StdCell* des_dff_way1 = getTechModel()->getStdCellLib()->createStdCell("DFFQ", des_dff_way1_name);
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des_dff_way1->construct();
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StdCell* des_latch = getTechModel()->getStdCellLib()->createStdCell("LATQ", des_latch_name);
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des_latch->construct();
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// Create clk divide circuit
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StdCell* ck_dff = getTechModel()->getStdCellLib()->createStdCell("DFFQ", ck_dff_name);
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ck_dff->construct();
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StdCell* ck_inv = getTechModel()->getStdCellLib()->createStdCell("INV", ck_inv_name);
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ck_inv->construct();
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// Connect ports
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portConnect(des_dff_way0, "CK", "InCK");
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portConnect(des_dff_way0, "D", mid_way0_name);
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portConnect(des_dff_way0, "Q", out_way0_name);
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portConnect(des_latch, "G", "InCK");
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portConnect(des_latch, "D", "In");
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portConnect(des_latch, "Q", mid_way0_name);
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portConnect(des_dff_way1, "CK", "InCK");
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portConnect(des_dff_way1, "D", "In");
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portConnect(des_dff_way1, "Q", out_way1_name);
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portConnect(ck_dff, "CK", "InCK");
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portConnect(ck_dff, "D", ck_div2_b_name);
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portConnect(ck_dff, "Q", ck_div2_name);
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portConnect(ck_inv, "A", ck_div2_name);
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portConnect(ck_inv, "Y", ck_div2_b_name);
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// Add sub instances
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addSubInstances(des_dff_way0, 1.0);
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addElectricalSubResults(des_dff_way0, 1.0);
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addSubInstances(des_dff_way1, 1.0);
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addElectricalSubResults(des_dff_way1, 1.0);
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addSubInstances(des_latch, 1.0);
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addElectricalSubResults(des_latch, 1.0);
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addSubInstances(ck_dff, 1.0);
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addElectricalSubResults(ck_dff, 1.0);
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addSubInstances(ck_inv, 1.0);
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addElectricalSubResults(ck_inv, 1.0);
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Result* deserialize = getEventResult("Deserialize");
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deserialize->addSubResult(des_dff_way0->getEventResult("CK"), des_dff_way0_name, 1.0);
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deserialize->addSubResult(des_dff_way0->getEventResult("DFFD"), des_dff_way0_name, 1.0);
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deserialize->addSubResult(des_dff_way0->getEventResult("DFFQ"), des_dff_way0_name, 1.0);
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deserialize->addSubResult(des_dff_way1->getEventResult("CK"), des_dff_way1_name, 1.0);
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deserialize->addSubResult(des_dff_way1->getEventResult("DFFD"), des_dff_way1_name, 1.0);
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deserialize->addSubResult(des_dff_way1->getEventResult("DFFQ"), des_dff_way1_name, 1.0);
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deserialize->addSubResult(des_latch->getEventResult("G"), des_latch_name, 1.0);
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deserialize->addSubResult(des_latch->getEventResult("LATD"), des_latch_name, 1.0);
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deserialize->addSubResult(des_latch->getEventResult("LATQ"), des_latch_name, 1.0);
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deserialize->addSubResult(ck_dff->getEventResult("CK"), ck_dff_name, 1.0);
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deserialize->addSubResult(ck_dff->getEventResult("DFFD"), ck_dff_name, 1.0);
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deserialize->addSubResult(ck_dff->getEventResult("DFFQ"), ck_dff_name, 1.0);
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deserialize->addSubResult(ck_inv->getEventResult("INV"), ck_inv_name, 1.0);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Create Sub-deserializers
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//-----------------------------------------------------------------
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// Create sub-deserializers
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const String& demux_way0_name = "DemuxTree_way0_" + (String) deserialization_ratio + "_to_1";
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const String& demux_way1_name = "DemuxTree_way1_" + (String) deserialization_ratio + "_to_1";
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DemuxTreeDeserializer* demux_way0 = new DemuxTreeDeserializer(demux_way0_name, getTechModel());
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demux_way0->setParameter("InDataRate", in_data_rate / 2.0);
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demux_way0->setParameter("OutDataRate", out_data_rate);
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demux_way0->setParameter("OutBits", out_bits / 2);
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demux_way0->setParameter("BitDuplicate", "TRUE");
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demux_way0->construct();
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DemuxTreeDeserializer* demux_way1 = new DemuxTreeDeserializer(demux_way1_name, getTechModel());
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demux_way1->setParameter("InDataRate", in_data_rate / 2.0);
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demux_way1->setParameter("OutDataRate", out_data_rate);
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demux_way1->setParameter("OutBits", out_bits / 2);
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demux_way1->setParameter("BitDuplicate", "TRUE");
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demux_way1->construct();
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// Connect ports
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portConnect(demux_way0, "In", out_way0_name);
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portConnect(demux_way0, "InCK", ck_div2_name);
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portConnect(demux_way0, "Out", "Out", makeNetIndex(0, out_bits/2-1));
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portConnect(demux_way1, "In", out_way1_name);
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portConnect(demux_way1, "InCK", ck_div2_name);
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portConnect(demux_way1, "Out", "Out", makeNetIndex(out_bits/2, out_bits-1));
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// Add subinstances and area results
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addSubInstances(demux_way0, 1.0);
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addElectricalSubResults(demux_way0, 1.0);
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addSubInstances(demux_way1, 1.0);
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addElectricalSubResults(demux_way1, 1.0);
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deserialize->addSubResult(demux_way0->getEventResult("Deserialize"), demux_way0_name, 1.0);
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deserialize->addSubResult(demux_way1->getEventResult("Deserialize"), demux_way1_name, 1.0);
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//-----------------------------------------------------------------
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}
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else if (bit_duplicate)
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{
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const String& demux_name = "DemuxTree_" + (String) deserialization_ratio + "_to_1";
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DemuxTreeDeserializer* des_bit = new DemuxTreeDeserializer(demux_name, getTechModel());
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des_bit->setParameter("InDataRate", in_data_rate);
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des_bit->setParameter("OutDataRate", out_data_rate);
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des_bit->setParameter("OutBits", deserialization_ratio);
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des_bit->setParameter("BitDuplicate", "TRUE");
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des_bit->construct();
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// Create VFI and VFO nets
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createNet("InVFI");
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createNet("OutVFO", makeNetIndex(0, deserialization_ratio-1));
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// Connect ports
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portConnect(des_bit, "In", "InVFI");
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portConnect(des_bit, "Out", "OutVFO");
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// Do VFI and VFO
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assignVirtualFanin("InVFI", "In");
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for (unsigned int i = 0; i < input_bits; ++i)
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{
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portConnect(des_bit, "InCK", "InCK");
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for (unsigned int j = 0; j < deserialization_ratio; ++j)
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assignVirtualFanout("Out", makeNetIndex(i*deserialization_ratio + j), "OutVFO", makeNetIndex(j));
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}
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// Add subinstances and area results
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addSubInstances(des_bit, input_bits);
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addElectricalSubResults(des_bit, input_bits);
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getEventResult("Deserialize")->addSubResult(des_bit->getEventResult("Deserialize"), demux_name, input_bits);
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}
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else
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{
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//Instantiate a bunch of 1 input bit deserializers
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for (unsigned int i = 0; i < input_bits; ++i)
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{
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const String& demux_name = "DemuxTree_" + (String) deserialization_ratio + "_to_1_bit" + (String) i;
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DemuxTreeDeserializer* des_bit = new DemuxTreeDeserializer(demux_name, getTechModel());
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des_bit->setParameter("InDataRate", in_data_rate);
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des_bit->setParameter("OutDataRate", out_data_rate);
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des_bit->setParameter("OutBits", deserialization_ratio);
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des_bit->setParameter("BitDuplicate", "TRUE");
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des_bit->construct();
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portConnect(des_bit, "In", "In", makeNetIndex(i));
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portConnect(des_bit, "InCK", "InCK");
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portConnect(des_bit, "Out", "Out", makeNetIndex(i*deserialization_ratio, (i+1)*deserialization_ratio-1));
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addSubInstances(des_bit, 1.0);
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addElectricalSubResults(des_bit, 1.0);
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getEventResult("Deserialize")->addSubResult(des_bit->getEventResult("Deserialize"), demux_name, 1.0);
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}
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}
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return;
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}
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void DemuxTreeDeserializer::propagateTransitionInfo()
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{
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// Get parameters
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bool bit_duplicate = getParameter("BitDuplicate");
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// Get generated properties
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unsigned int deserialization_ratio = getGenProperties()->get("DeserializationRatio");
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unsigned int input_bits = getGenProperties()->get("InputBits");
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// Calculate output transitions and activities
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if (deserialization_ratio == 1)
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{
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// If no deserialization, then just propagate input transition info to output port
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propagatePortTransitionInfo("Out", "In");
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}
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else if (input_bits == 1)
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{
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const String& des_dff_way0_name = "DesDFFWay0";
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const String& des_dff_way1_name = "DesDFFWay1";
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const String& des_latch_name = "DesLatch";
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const String& ck_dff_name = "CKDFF";
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const String& ck_inv_name = "CKINV";
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// Sub-deserializer names
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const String& demux_way0_name = "DemuxTree_way0_" + (String) deserialization_ratio + "_to_1";
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const String& demux_way1_name = "DemuxTree_way1_" + (String) deserialization_ratio + "_to_1";
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// Update transition info for deserialization registers/latches
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ElectricalModel* des_latch = (ElectricalModel*) getSubInstance(des_latch_name);
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propagatePortTransitionInfo(des_latch, "G", "InCK");
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propagatePortTransitionInfo(des_latch, "D", "In");
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des_latch->use();
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ElectricalModel* des_dff_way0 = (ElectricalModel*) getSubInstance(des_dff_way0_name);
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propagatePortTransitionInfo(des_dff_way0, "CK", "InCK");
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propagatePortTransitionInfo(des_dff_way0, "D", des_latch, "Q");
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des_dff_way0->use();
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ElectricalModel* des_dff_way1 = (ElectricalModel*) getSubInstance(des_dff_way1_name);
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propagatePortTransitionInfo(des_dff_way1, "CK", "InCK");
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propagatePortTransitionInfo(des_dff_way1, "D", "In");
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des_dff_way1->use();
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// Get input transitions of input clock
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double P01_CK = getInputPort("InCK")->getTransitionInfo().getNumberTransitions01();
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// Update transition info for clk division DFF
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ElectricalModel* ck_dff = (ElectricalModel*) getSubInstance(ck_dff_name);
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propagatePortTransitionInfo(ck_dff, "CK", "InCK");
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// Since it is a clock divider, P01 is D and Q are simply half the P01 of D and Q of
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// the input clock
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if (P01_CK != 0) ck_dff->getInputPort("D")->setTransitionInfo(TransitionInfo(0.0, P01_CK * 0.5, 0.0));
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else ck_dff->getInputPort("D")->setTransitionInfo(TransitionInfo(0.5, 0.0, 0.5));
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ck_dff->use();
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// Update transition info of clk divided inverter
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ElectricalModel* ck_inv = (ElectricalModel*) getSubInstance(ck_inv_name);
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propagatePortTransitionInfo(ck_inv, "A", ck_dff, "Q");
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ck_inv->use();
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// Update transition info for next demux stages
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ElectricalModel* demux_way0 = (ElectricalModel*) getSubInstance(demux_way0_name);
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propagatePortTransitionInfo(demux_way0, "In", des_dff_way0, "Q");
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propagatePortTransitionInfo(demux_way0, "InCK", ck_dff, "Q");
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demux_way0->use();
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ElectricalModel* demux_way1 = (ElectricalModel*) getSubInstance(demux_way1_name);
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propagatePortTransitionInfo(demux_way1, "In", des_dff_way1, "Q");
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propagatePortTransitionInfo(demux_way1, "InCK", ck_dff, "Q");
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demux_way1->use();
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propagatePortTransitionInfo("Out", demux_way0, "Out");
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}
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else if (bit_duplicate)
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{
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// Propagate transition info
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const String& demux_name = "DemuxTree_" + (String) deserialization_ratio + "_to_1";
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ElectricalModel* demux = (ElectricalModel*) getSubInstance(demux_name);
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propagatePortTransitionInfo(demux, "In", "In");
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propagatePortTransitionInfo(demux, "InCK", "InCK");
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demux->use();
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propagatePortTransitionInfo("Out", demux, "Out");
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}
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else
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{
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// Set output probability to be average that of probabilties of each output bit
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// Update all 1 bit deserializers
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for (unsigned int i = 0; i < input_bits; ++i)
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{
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const String& demux_name = "DemuxTree_" + (String) deserialization_ratio + "_to_1_bit" + (String) i;
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ElectricalModel* demux_bit = (ElectricalModel*) getSubInstance(demux_name);
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propagatePortTransitionInfo(demux_bit, "In", "In");
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propagatePortTransitionInfo(demux_bit, "InCK", "InCK");
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demux_bit->use();
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propagatePortTransitionInfo("Out", demux_bit, "Out");
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}
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}
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return;
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}
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} // namespace DSENT
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