1814a85a05
Previously, the O3 CPU could stop in the middle of a microcode sequence. This patch makes sure that the pipeline stops when it has committed a normal instruction or exited from a microcode sequence. Additionally, it makes sure that the pipeline has no instructions in flight when it is drained, which should make draining more robust. Draining is controlled in the commit stage, which checks if the next PC after a committed instruction is in microcode. If this isn't the case, it requests a squash of all instructions after that the instruction that just committed and immediately signals a drain stall to the fetch stage. The CPU then continues to execute until the pipeline and all associated buffers are empty.
597 lines
18 KiB
C++
597 lines
18 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include <map>
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#include "cpu/o3/inst_queue.hh"
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#include "cpu/o3/mem_dep_unit.hh"
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#include "debug/MemDepUnit.hh"
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#include "params/DerivO3CPU.hh"
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template <class MemDepPred, class Impl>
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MemDepUnit<MemDepPred, Impl>::MemDepUnit()
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: loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
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storeBarrierSN(0), iqPtr(NULL)
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{
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}
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template <class MemDepPred, class Impl>
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MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
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: _name(params->name + ".memdepunit"),
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depPred(params->store_set_clear_period, params->SSITSize,
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params->LFSTSize),
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loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
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storeBarrierSN(0), iqPtr(NULL)
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{
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DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
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}
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template <class MemDepPred, class Impl>
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MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
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{
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for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
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ListIt inst_list_it = instList[tid].begin();
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MemDepHashIt hash_it;
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while (!instList[tid].empty()) {
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hash_it = memDepHash.find((*inst_list_it)->seqNum);
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assert(hash_it != memDepHash.end());
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memDepHash.erase(hash_it);
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instList[tid].erase(inst_list_it++);
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}
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}
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#ifdef DEBUG
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assert(MemDepEntry::memdep_count == 0);
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#endif
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
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{
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DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
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_name = csprintf("%s.memDep%d", params->name, tid);
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id = tid;
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depPred.init(params->store_set_clear_period, params->SSITSize,
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params->LFSTSize);
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::regStats()
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{
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insertedLoads
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.name(name() + ".insertedLoads")
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.desc("Number of loads inserted to the mem dependence unit.");
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insertedStores
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.name(name() + ".insertedStores")
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.desc("Number of stores inserted to the mem dependence unit.");
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conflictingLoads
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.name(name() + ".conflictingLoads")
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.desc("Number of conflicting loads.");
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conflictingStores
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.name(name() + ".conflictingStores")
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.desc("Number of conflicting stores.");
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::drainSanityCheck() const
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{
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assert(instsToReplay.empty());
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assert(memDepHash.empty());
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for (int i = 0; i < Impl::MaxThreads; ++i)
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assert(instList[i].empty());
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assert(instsToReplay.empty());
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assert(memDepHash.empty());
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::takeOverFrom()
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{
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// Be sure to reset all state.
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loadBarrier = storeBarrier = false;
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loadBarrierSN = storeBarrierSN = 0;
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depPred.clear();
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
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{
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iqPtr = iq_ptr;
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
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{
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ThreadID tid = inst->threadNumber;
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MemDepEntryPtr inst_entry = new MemDepEntry(inst);
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// Add the MemDepEntry to the hash.
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memDepHash.insert(
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std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
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#ifdef DEBUG
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MemDepEntry::memdep_insert++;
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#endif
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instList[tid].push_back(inst);
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inst_entry->listIt = --(instList[tid].end());
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// Check any barriers and the dependence predictor for any
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// producing memrefs/stores.
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InstSeqNum producing_store;
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if (inst->isLoad() && loadBarrier) {
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DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
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loadBarrierSN);
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producing_store = loadBarrierSN;
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} else if (inst->isStore() && storeBarrier) {
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DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
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storeBarrierSN);
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producing_store = storeBarrierSN;
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} else {
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producing_store = depPred.checkInst(inst->instAddr());
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}
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MemDepEntryPtr store_entry = NULL;
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// If there is a producing store, try to find the entry.
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if (producing_store != 0) {
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DPRINTF(MemDepUnit, "Searching for producer\n");
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MemDepHashIt hash_it = memDepHash.find(producing_store);
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if (hash_it != memDepHash.end()) {
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store_entry = (*hash_it).second;
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DPRINTF(MemDepUnit, "Proucer found\n");
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}
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}
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// If no store entry, then instruction can issue as soon as the registers
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// are ready.
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if (!store_entry) {
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DPRINTF(MemDepUnit, "No dependency for inst PC "
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"%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
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inst_entry->memDepReady = true;
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if (inst->readyToIssue()) {
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inst_entry->regsReady = true;
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moveToReady(inst_entry);
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}
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} else {
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// Otherwise make the instruction dependent on the store/barrier.
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DPRINTF(MemDepUnit, "Adding to dependency list; "
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"inst PC %s is dependent on [sn:%lli].\n",
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inst->pcState(), producing_store);
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if (inst->readyToIssue()) {
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inst_entry->regsReady = true;
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}
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// Clear the bit saying this instruction can issue.
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inst->clearCanIssue();
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// Add this instruction to the list of dependents.
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store_entry->dependInsts.push_back(inst_entry);
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if (inst->isLoad()) {
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++conflictingLoads;
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} else {
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++conflictingStores;
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}
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}
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if (inst->isStore()) {
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DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
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inst->pcState(), inst->seqNum);
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depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
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++insertedStores;
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} else if (inst->isLoad()) {
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++insertedLoads;
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} else {
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panic("Unknown type! (most likely a barrier).");
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
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{
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ThreadID tid = inst->threadNumber;
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MemDepEntryPtr inst_entry = new MemDepEntry(inst);
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// Insert the MemDepEntry into the hash.
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memDepHash.insert(
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std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
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#ifdef DEBUG
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MemDepEntry::memdep_insert++;
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#endif
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// Add the instruction to the list.
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instList[tid].push_back(inst);
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inst_entry->listIt = --(instList[tid].end());
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// Might want to turn this part into an inline function or something.
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// It's shared between both insert functions.
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if (inst->isStore()) {
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DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
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inst->pcState(), inst->seqNum);
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depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
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++insertedStores;
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} else if (inst->isLoad()) {
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++insertedLoads;
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} else {
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panic("Unknown type! (most likely a barrier).");
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
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{
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InstSeqNum barr_sn = barr_inst->seqNum;
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// Memory barriers block loads and stores, write barriers only stores.
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if (barr_inst->isMemBarrier()) {
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loadBarrier = true;
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loadBarrierSN = barr_sn;
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storeBarrier = true;
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storeBarrierSN = barr_sn;
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DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
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barr_inst->pcState(),barr_sn);
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} else if (barr_inst->isWriteBarrier()) {
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storeBarrier = true;
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storeBarrierSN = barr_sn;
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DPRINTF(MemDepUnit, "Inserted a write barrier\n");
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}
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ThreadID tid = barr_inst->threadNumber;
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MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
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// Add the MemDepEntry to the hash.
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memDepHash.insert(
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std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
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#ifdef DEBUG
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MemDepEntry::memdep_insert++;
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#endif
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// Add the instruction to the instruction list.
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instList[tid].push_back(barr_inst);
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inst_entry->listIt = --(instList[tid].end());
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
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{
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DPRINTF(MemDepUnit, "Marking registers as ready for "
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"instruction PC %s [sn:%lli].\n",
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inst->pcState(), inst->seqNum);
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MemDepEntryPtr inst_entry = findInHash(inst);
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inst_entry->regsReady = true;
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if (inst_entry->memDepReady) {
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DPRINTF(MemDepUnit, "Instruction has its memory "
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"dependencies resolved, adding it to the ready list.\n");
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moveToReady(inst_entry);
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} else {
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DPRINTF(MemDepUnit, "Instruction still waiting on "
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"memory dependency.\n");
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
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{
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DPRINTF(MemDepUnit, "Marking non speculative "
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"instruction PC %s as ready [sn:%lli].\n",
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inst->pcState(), inst->seqNum);
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MemDepEntryPtr inst_entry = findInHash(inst);
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moveToReady(inst_entry);
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
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{
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instsToReplay.push_back(inst);
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
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{
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DynInstPtr temp_inst;
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// For now this replay function replays all waiting memory ops.
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while (!instsToReplay.empty()) {
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temp_inst = instsToReplay.front();
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MemDepEntryPtr inst_entry = findInHash(temp_inst);
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DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
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temp_inst->pcState(), temp_inst->seqNum);
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moveToReady(inst_entry);
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instsToReplay.pop_front();
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
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{
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DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
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inst->pcState(), inst->seqNum);
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ThreadID tid = inst->threadNumber;
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// Remove the instruction from the hash and the list.
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MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
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assert(hash_it != memDepHash.end());
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instList[tid].erase((*hash_it).second->listIt);
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(*hash_it).second = NULL;
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memDepHash.erase(hash_it);
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#ifdef DEBUG
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MemDepEntry::memdep_erase++;
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#endif
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
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{
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wakeDependents(inst);
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completed(inst);
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InstSeqNum barr_sn = inst->seqNum;
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DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
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inst->seqNum);
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if (inst->isMemBarrier()) {
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if (loadBarrierSN == barr_sn)
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loadBarrier = false;
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if (storeBarrierSN == barr_sn)
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storeBarrier = false;
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} else if (inst->isWriteBarrier()) {
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if (storeBarrierSN == barr_sn)
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storeBarrier = false;
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
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{
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// Only stores and barriers have dependents.
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if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
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return;
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}
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MemDepEntryPtr inst_entry = findInHash(inst);
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for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
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MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
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if (!woken_inst->inst) {
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// Potentially removed mem dep entries could be on this list
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continue;
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}
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DPRINTF(MemDepUnit, "Waking up a dependent inst, "
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"[sn:%lli].\n",
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woken_inst->inst->seqNum);
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if (woken_inst->regsReady && !woken_inst->squashed) {
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moveToReady(woken_inst);
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} else {
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woken_inst->memDepReady = true;
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}
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}
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inst_entry->dependInsts.clear();
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
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ThreadID tid)
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{
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if (!instsToReplay.empty()) {
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ListIt replay_it = instsToReplay.begin();
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while (replay_it != instsToReplay.end()) {
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if ((*replay_it)->threadNumber == tid &&
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(*replay_it)->seqNum > squashed_num) {
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instsToReplay.erase(replay_it++);
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} else {
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++replay_it;
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}
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}
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}
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ListIt squash_it = instList[tid].end();
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--squash_it;
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MemDepHashIt hash_it;
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while (!instList[tid].empty() &&
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(*squash_it)->seqNum > squashed_num) {
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DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
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(*squash_it)->seqNum);
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if ((*squash_it)->seqNum == loadBarrierSN)
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loadBarrier = false;
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if ((*squash_it)->seqNum == storeBarrierSN)
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storeBarrier = false;
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hash_it = memDepHash.find((*squash_it)->seqNum);
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assert(hash_it != memDepHash.end());
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(*hash_it).second->squashed = true;
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(*hash_it).second = NULL;
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memDepHash.erase(hash_it);
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#ifdef DEBUG
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MemDepEntry::memdep_erase++;
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#endif
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instList[tid].erase(squash_it--);
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}
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// Tell the dependency predictor to squash as well.
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depPred.squash(squashed_num, tid);
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
|
|
DynInstPtr &violating_load)
|
|
{
|
|
DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
|
|
" load: %#x, store: %#x\n", violating_load->instAddr(),
|
|
store_inst->instAddr());
|
|
// Tell the memory dependence unit of the violation.
|
|
depPred.violation(store_inst->instAddr(), violating_load->instAddr());
|
|
}
|
|
|
|
template <class MemDepPred, class Impl>
|
|
void
|
|
MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
|
|
{
|
|
DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
|
|
inst->instAddr(), inst->seqNum);
|
|
|
|
depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
|
|
}
|
|
|
|
template <class MemDepPred, class Impl>
|
|
inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
|
|
MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
|
|
{
|
|
MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
|
|
|
|
assert(hash_it != memDepHash.end());
|
|
|
|
return (*hash_it).second;
|
|
}
|
|
|
|
template <class MemDepPred, class Impl>
|
|
inline void
|
|
MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
|
|
{
|
|
DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
|
|
"to the ready list.\n", woken_inst_entry->inst->seqNum);
|
|
|
|
assert(!woken_inst_entry->squashed);
|
|
|
|
iqPtr->addReadyMemInst(woken_inst_entry->inst);
|
|
}
|
|
|
|
|
|
template <class MemDepPred, class Impl>
|
|
void
|
|
MemDepUnit<MemDepPred, Impl>::dumpLists()
|
|
{
|
|
for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
|
|
cprintf("Instruction list %i size: %i\n",
|
|
tid, instList[tid].size());
|
|
|
|
ListIt inst_list_it = instList[tid].begin();
|
|
int num = 0;
|
|
|
|
while (inst_list_it != instList[tid].end()) {
|
|
cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
|
|
"Squashed:%i\n\n",
|
|
num, (*inst_list_it)->pcState(),
|
|
(*inst_list_it)->seqNum,
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->isIssued(),
|
|
(*inst_list_it)->isSquashed());
|
|
inst_list_it++;
|
|
++num;
|
|
}
|
|
}
|
|
|
|
cprintf("Memory dependence hash size: %i\n", memDepHash.size());
|
|
|
|
#ifdef DEBUG
|
|
cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
|
|
#endif
|
|
}
|