1b370431d0
While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe. After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc when running twolf for ARM.
698 lines
21 KiB
C++
698 lines
21 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_OZONE_LW_LSQ_HH__
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#define __CPU_OZONE_LW_LSQ_HH__
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#include <algorithm>
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#include <list>
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#include <map>
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#include <queue>
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#include "arch/types.hh"
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#include "base/hashmap.hh"
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#include "config/the_isa.hh"
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#include "cpu/inst_seq.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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//#include "mem/page_table.hh"
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#include "sim/debug.hh"
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#include "sim/fault_fwd.hh"
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#include "sim/sim_object.hh"
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class MemObject;
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/**
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* Class that implements the actual LQ and SQ for each specific thread.
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* Both are circular queues; load entries are freed upon committing, while
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* store entries are freed once they writeback. The LSQUnit tracks if there
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* are memory ordering violations, and also detects partial load to store
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* forwarding cases (a store only has part of a load's data) that requires
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* the load to wait until the store writes back. In the former case it
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* holds onto the instruction until the dependence unit looks at it, and
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* in the latter it stalls the LSQ until the store writes back. At that
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* point the load is replayed.
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*/
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template <class Impl>
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class OzoneLWLSQ {
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::OzoneCPU OzoneCPU;
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typedef typename Impl::BackEnd BackEnd;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::IssueStruct IssueStruct;
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typedef TheISA::IntReg IntReg;
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typedef typename std::map<InstSeqNum, DynInstPtr>::iterator LdMapIt;
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public:
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/** Constructs an LSQ unit. init() must be called prior to use. */
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OzoneLWLSQ();
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/** Initializes the LSQ unit with the specified number of entries. */
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void init(Params *params, unsigned maxLQEntries,
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unsigned maxSQEntries, unsigned id);
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/** Returns the name of the LSQ unit. */
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std::string name() const;
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void regStats();
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/** Sets the CPU pointer. */
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void setCPU(OzoneCPU *cpu_ptr);
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/** Sets the back-end stage pointer. */
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void setBE(BackEnd *be_ptr)
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{ be = be_ptr; }
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Port *getDcachePort() { return &dcachePort; }
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/** Ticks the LSQ unit, which in this case only resets the number of
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* used cache ports.
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* @todo: Move the number of used ports up to the LSQ level so it can
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* be shared by all LSQ units.
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*/
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void tick() { usedPorts = 0; }
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/** Inserts an instruction. */
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void insert(DynInstPtr &inst);
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/** Inserts a load instruction. */
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void insertLoad(DynInstPtr &load_inst);
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/** Inserts a store instruction. */
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void insertStore(DynInstPtr &store_inst);
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/** Executes a load instruction. */
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Fault executeLoad(DynInstPtr &inst);
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/** Executes a store instruction. */
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Fault executeStore(DynInstPtr &inst);
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/** Commits the head load. */
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void commitLoad();
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/** Commits loads older than a specific sequence number. */
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void commitLoads(InstSeqNum &youngest_inst);
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/** Commits stores older than a specific sequence number. */
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void commitStores(InstSeqNum &youngest_inst);
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/** Writes back stores. */
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void writebackStores();
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/** Completes the data access that has been returned from the
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* memory system. */
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void completeDataAccess(PacketPtr pkt);
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// @todo: Include stats in the LSQ unit.
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//void regStats();
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/** Clears all the entries in the LQ. */
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void clearLQ();
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/** Clears all the entries in the SQ. */
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void clearSQ();
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/** Resizes the LQ to a given size. */
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void resizeLQ(unsigned size);
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/** Resizes the SQ to a given size. */
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void resizeSQ(unsigned size);
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/** Squashes all instructions younger than a specific sequence number. */
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void squash(const InstSeqNum &squashed_num);
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/** Returns if there is a memory ordering violation. Value is reset upon
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* call to getMemDepViolator().
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*/
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bool violation() { return memDepViolator; }
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/** Returns the memory ordering violator. */
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DynInstPtr getMemDepViolator();
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/** Returns if a load became blocked due to the memory system. It clears
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* the bool's value upon this being called.
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*/
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bool loadBlocked()
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{ return isLoadBlocked; }
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void clearLoadBlocked()
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{ isLoadBlocked = false; }
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bool isLoadBlockedHandled()
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{ return loadBlockedHandled; }
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void setLoadBlockedHandled()
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{ loadBlockedHandled = true; }
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/** Returns the number of free entries (min of free LQ and SQ entries). */
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unsigned numFreeEntries();
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/** Returns the number of loads ready to execute. */
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int numLoadsReady();
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/** Returns the number of loads in the LQ. */
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int numLoads() { return loads; }
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/** Returns the number of stores in the SQ. */
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int numStores() { return stores + storesInFlight; }
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/** Returns if either the LQ or SQ is full. */
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bool isFull() { return lqFull() || sqFull(); }
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/** Returns if the LQ is full. */
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bool lqFull() { return loads >= (LQEntries - 1); }
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/** Returns if the SQ is full. */
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bool sqFull() { return (stores + storesInFlight) >= (SQEntries - 1); }
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/** Debugging function to dump instructions in the LSQ. */
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void dumpInsts();
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/** Returns the number of instructions in the LSQ. */
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unsigned getCount() { return loads + stores; }
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/** Returns if there are any stores to writeback. */
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bool hasStoresToWB() { return storesToWB; }
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/** Returns the number of stores to writeback. */
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int numStoresToWB() { return storesToWB; }
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/** Returns if the LSQ unit will writeback on this cycle. */
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bool willWB() { return storeQueue.back().canWB &&
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!storeQueue.back().completed &&
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!isStoreBlocked; }
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void switchOut();
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void takeOverFrom(ThreadContext *old_tc = NULL);
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bool isSwitchedOut() { return switchedOut; }
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bool switchedOut;
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private:
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/** Writes back the instruction, sending it to IEW. */
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void writeback(DynInstPtr &inst, PacketPtr pkt);
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/** Handles completing the send of a store to memory. */
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void storePostSend(PacketPtr pkt, DynInstPtr &inst);
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/** Completes the store at the specified index. */
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void completeStore(DynInstPtr &inst);
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void removeStore(int store_idx);
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/** Handles doing the retry. */
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void recvRetry();
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private:
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/** Pointer to the CPU. */
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OzoneCPU *cpu;
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/** Pointer to the back-end stage. */
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BackEnd *be;
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class DcachePort : public MasterPort
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{
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protected:
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OzoneLWLSQ *lsq;
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public:
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DcachePort(OzoneLWLSQ *_lsq)
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: lsq(_lsq)
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{ }
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protected:
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual void recvFunctional(PacketPtr pkt);
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/**
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* Is a snooper due to LSQ maintenance
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*/
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virtual bool isSnooping() const { return true; }
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virtual bool recvTiming(PacketPtr pkt);
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virtual void recvRetry();
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};
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/** D-cache port. */
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DcachePort dcachePort;
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public:
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struct SQEntry {
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/** Constructs an empty store queue entry. */
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SQEntry()
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: inst(NULL), req(NULL), size(0), data(0),
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canWB(0), committed(0), completed(0), lqIt(NULL)
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{ }
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/** Constructs a store queue entry for a given instruction. */
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SQEntry(DynInstPtr &_inst)
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: inst(_inst), req(NULL), size(0), data(0),
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canWB(0), committed(0), completed(0), lqIt(NULL)
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{ }
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/** The store instruction. */
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DynInstPtr inst;
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/** The memory request for the store. */
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RequestPtr req;
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/** The size of the store. */
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int size;
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/** The store data. */
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IntReg data;
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/** Whether or not the store can writeback. */
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bool canWB;
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/** Whether or not the store is committed. */
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bool committed;
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/** Whether or not the store is completed. */
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bool completed;
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typename std::list<DynInstPtr>::iterator lqIt;
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};
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/** Derived class to hold any sender state the LSQ needs. */
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class LSQSenderState : public Packet::SenderState
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{
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public:
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/** Default constructor. */
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LSQSenderState()
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: noWB(false)
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{ }
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/** Instruction who initiated the access to memory. */
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DynInstPtr inst;
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/** Whether or not it is a load. */
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bool isLoad;
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/** The LQ/SQ index of the instruction. */
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int idx;
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/** Whether or not the instruction will need to writeback. */
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bool noWB;
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};
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/** Writeback event, specifically for when stores forward data to loads. */
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class WritebackEvent : public Event {
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public:
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/** Constructs a writeback event. */
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WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, OzoneLWLSQ *lsq_ptr);
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/** Processes the writeback event. */
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void process();
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/** Returns the description of this event. */
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const char *description() const;
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private:
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/** Instruction whose results are being written back. */
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DynInstPtr inst;
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/** The packet that would have been sent to memory. */
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PacketPtr pkt;
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/** The pointer to the LSQ unit that issued the store. */
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OzoneLWLSQ<Impl> *lsqPtr;
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};
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enum Status {
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Running,
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Idle,
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DcacheMissStall,
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DcacheMissSwitch
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};
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private:
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/** The OzoneLWLSQ thread id. */
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unsigned lsqID;
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/** The status of the LSQ unit. */
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Status _status;
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/** The store queue. */
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std::list<SQEntry> storeQueue;
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/** The load queue. */
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std::list<DynInstPtr> loadQueue;
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typedef typename std::list<SQEntry>::iterator SQIt;
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typedef typename std::list<DynInstPtr>::iterator LQIt;
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struct HashFn {
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size_t operator() (const int a) const
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{
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unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
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return hash;
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}
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};
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m5::hash_map<int, SQIt, HashFn> SQItHash;
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std::queue<int> SQIndices;
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m5::hash_map<int, LQIt, HashFn> LQItHash;
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std::queue<int> LQIndices;
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typedef typename m5::hash_map<int, LQIt, HashFn>::iterator LQHashIt;
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typedef typename m5::hash_map<int, SQIt, HashFn>::iterator SQHashIt;
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// Consider making these 16 bits
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/** The number of LQ entries. */
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unsigned LQEntries;
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/** The number of SQ entries. */
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unsigned SQEntries;
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/** The number of load instructions in the LQ. */
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int loads;
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/** The number of store instructions in the SQ (excludes those waiting to
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* writeback).
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*/
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int stores;
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int storesToWB;
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public:
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int storesInFlight;
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private:
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/// @todo Consider moving to a more advanced model with write vs read ports
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/** The number of cache ports available each cycle. */
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int cachePorts;
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/** The number of used cache ports in this cycle. */
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int usedPorts;
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//list<InstSeqNum> mshrSeqNums;
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/** Tota number of memory ordering violations. */
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Stats::Scalar lsqMemOrderViolation;
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//Stats::Scalar dcacheStallCycles;
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Counter lastDcacheStall;
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// Make these per thread?
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/** Whether or not the LSQ is stalled. */
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bool stalled;
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/** The store that causes the stall due to partial store to load
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* forwarding.
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*/
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InstSeqNum stallingStoreIsn;
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/** The index of the above store. */
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LQIt stallingLoad;
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/** The packet that needs to be retried. */
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PacketPtr retryPkt;
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/** Whehter or not a store is blocked due to the memory system. */
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bool isStoreBlocked;
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/** Whether or not a load is blocked due to the memory system. It is
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* cleared when this value is checked via loadBlocked().
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*/
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bool isLoadBlocked;
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bool loadBlockedHandled;
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InstSeqNum blockedLoadSeqNum;
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/** The oldest faulting load instruction. */
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DynInstPtr loadFaultInst;
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/** The oldest faulting store instruction. */
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DynInstPtr storeFaultInst;
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/** The oldest load that caused a memory ordering violation. */
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DynInstPtr memDepViolator;
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// Will also need how many read/write ports the Dcache has. Or keep track
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// of that in stage that is one level up, and only call executeLoad/Store
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// the appropriate number of times.
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public:
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/** Executes the load at the given index. */
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template <class T>
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Fault read(RequestPtr req, T &data, int load_idx);
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/** Executes the store at the given index. */
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template <class T>
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Fault write(RequestPtr req, T &data, int store_idx);
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/** Returns the sequence number of the head load instruction. */
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InstSeqNum getLoadHeadSeqNum()
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{
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if (!loadQueue.empty()) {
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return loadQueue.back()->seqNum;
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} else {
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return 0;
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}
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}
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/** Returns the sequence number of the head store instruction. */
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InstSeqNum getStoreHeadSeqNum()
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{
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if (!storeQueue.empty()) {
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return storeQueue.back().inst->seqNum;
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} else {
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return 0;
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}
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}
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/** Returns whether or not the LSQ unit is stalled. */
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bool isStalled() { return stalled; }
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};
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template <class Impl>
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template <class T>
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Fault
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OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
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{
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//Depending on issue2execute delay a squashed load could
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//execute if it is found to be squashed in the same
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//cycle it is scheduled to execute
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typename m5::hash_map<int, LQIt, HashFn>::iterator
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lq_hash_it = LQItHash.find(load_idx);
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assert(lq_hash_it != LQItHash.end());
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DynInstPtr inst = (*(*lq_hash_it).second);
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// Make sure this isn't an uncacheable access
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// A bit of a hackish way to get uncached accesses to work only if they're
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// at the head of the LSQ and are ready to commit (at the head of the ROB
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// too).
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// @todo: Fix uncached accesses.
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if (req->isUncacheable() &&
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(inst != loadQueue.back() || !inst->isAtCommit())) {
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DPRINTF(OzoneLSQ, "[sn:%lli] Uncached load and not head of "
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"commit/LSQ!\n",
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inst->seqNum);
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be->rescheduleMemInst(inst);
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return TheISA::genMachineCheckFault();
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}
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// Check the SQ for any previous stores that might lead to forwarding
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SQIt sq_it = storeQueue.begin();
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int store_size = 0;
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DPRINTF(OzoneLSQ, "Read called, load idx: %i addr: %#x\n",
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load_idx, req->getPaddr());
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while (sq_it != storeQueue.end() && (*sq_it).inst->seqNum > inst->seqNum)
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++sq_it;
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while (1) {
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// End once we've reached the top of the LSQ
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if (sq_it == storeQueue.end()) {
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break;
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}
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assert((*sq_it).inst);
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store_size = (*sq_it).size;
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if (store_size == 0 || (*sq_it).committed) {
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sq_it++;
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continue;
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}
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// Check if the store data is within the lower and upper bounds of
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// addresses that the request needs.
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bool store_has_lower_limit =
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req->getVaddr() >= (*sq_it).inst->effAddr;
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bool store_has_upper_limit =
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(req->getVaddr() + req->getSize()) <= ((*sq_it).inst->effAddr +
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store_size);
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bool lower_load_has_store_part =
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req->getVaddr() < ((*sq_it).inst->effAddr +
|
|
store_size);
|
|
bool upper_load_has_store_part =
|
|
(req->getVaddr() + req->getSize()) > (*sq_it).inst->effAddr;
|
|
|
|
// If the store's data has all of the data needed, we can forward.
|
|
if (store_has_lower_limit && store_has_upper_limit) {
|
|
int shift_amt = req->getVaddr() & (store_size - 1);
|
|
// Assumes byte addressing
|
|
shift_amt = shift_amt << 3;
|
|
|
|
// Cast this to type T?
|
|
data = (*sq_it).data >> shift_amt;
|
|
|
|
assert(!inst->memData);
|
|
inst->memData = new uint8_t[64];
|
|
|
|
memcpy(inst->memData, &data, req->getSize());
|
|
|
|
DPRINTF(OzoneLSQ, "Forwarding from store [sn:%lli] to load to "
|
|
"[sn:%lli] addr %#x, data %#x\n",
|
|
(*sq_it).inst->seqNum, inst->seqNum, req->getVaddr(),
|
|
*(inst->memData));
|
|
|
|
PacketPtr data_pkt = new Packet(req, Packet::ReadReq);
|
|
data_pkt->dataStatic(inst->memData);
|
|
|
|
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
|
|
|
|
// We'll say this has a 1 cycle load-store forwarding latency
|
|
// for now.
|
|
// @todo: Need to make this a parameter.
|
|
wb->schedule(curTick());
|
|
|
|
// Should keep track of stat for forwarded data
|
|
return NoFault;
|
|
} else if ((store_has_lower_limit && lower_load_has_store_part) ||
|
|
(store_has_upper_limit && upper_load_has_store_part) ||
|
|
(lower_load_has_store_part && upper_load_has_store_part)) {
|
|
// This is the partial store-load forwarding case where a store
|
|
// has only part of the load's data.
|
|
|
|
// If it's already been written back, then don't worry about
|
|
// stalling on it.
|
|
if ((*sq_it).completed) {
|
|
sq_it++;
|
|
break;
|
|
}
|
|
|
|
// Must stall load and force it to retry, so long as it's the oldest
|
|
// load that needs to do so.
|
|
if (!stalled ||
|
|
(stalled &&
|
|
inst->seqNum <
|
|
(*stallingLoad)->seqNum)) {
|
|
stalled = true;
|
|
stallingStoreIsn = (*sq_it).inst->seqNum;
|
|
stallingLoad = (*lq_hash_it).second;
|
|
}
|
|
|
|
// Tell IQ/mem dep unit that this instruction will need to be
|
|
// rescheduled eventually
|
|
be->rescheduleMemInst(inst);
|
|
|
|
DPRINTF(OzoneLSQ, "Load-store forwarding mis-match. "
|
|
"Store [sn:%lli] to load addr %#x\n",
|
|
(*sq_it).inst->seqNum, req->getVaddr());
|
|
|
|
return NoFault;
|
|
}
|
|
sq_it++;
|
|
}
|
|
|
|
// If there's no forwarding case, then go access memory
|
|
DPRINTF(OzoneLSQ, "Doing functional access for inst PC %#x\n",
|
|
inst->readPC());
|
|
|
|
assert(!inst->memData);
|
|
inst->memData = new uint8_t[64];
|
|
|
|
++usedPorts;
|
|
|
|
DPRINTF(OzoneLSQ, "Doing timing access for inst PC %#x\n",
|
|
inst->readPC());
|
|
|
|
PacketPtr data_pkt =
|
|
new Packet(req,
|
|
(req->isLLSC() ?
|
|
MemCmd::LoadLockedReq : Packet::ReadReq));
|
|
data_pkt->dataStatic(inst->memData);
|
|
|
|
LSQSenderState *state = new LSQSenderState;
|
|
state->isLoad = true;
|
|
state->idx = load_idx;
|
|
state->inst = inst;
|
|
data_pkt->senderState = state;
|
|
|
|
// if we have a cache, do cache access too
|
|
if (!dcachePort.sendTiming(data_pkt)) {
|
|
// There's an older load that's already going to squash.
|
|
if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
|
|
return NoFault;
|
|
|
|
// Record that the load was blocked due to memory. This
|
|
// load will squash all instructions after it, be
|
|
// refetched, and re-executed.
|
|
isLoadBlocked = true;
|
|
loadBlockedHandled = false;
|
|
blockedLoadSeqNum = inst->seqNum;
|
|
// No fault occurred, even though the interface is blocked.
|
|
return NoFault;
|
|
}
|
|
|
|
if (req->isLLSC()) {
|
|
cpu->lockFlag = true;
|
|
}
|
|
|
|
return NoFault;
|
|
}
|
|
|
|
template <class Impl>
|
|
template <class T>
|
|
Fault
|
|
OzoneLWLSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
|
|
{
|
|
SQHashIt sq_hash_it = SQItHash.find(store_idx);
|
|
assert(sq_hash_it != SQItHash.end());
|
|
|
|
SQIt sq_it = (*sq_hash_it).second;
|
|
assert((*sq_it).inst);
|
|
|
|
DPRINTF(OzoneLSQ, "Doing write to store idx %i, addr %#x data %#x"
|
|
" | [sn:%lli]\n",
|
|
store_idx, req->getPaddr(), data, (*sq_it).inst->seqNum);
|
|
|
|
(*sq_it).req = req;
|
|
(*sq_it).size = sizeof(T);
|
|
(*sq_it).data = data;
|
|
/*
|
|
assert(!req->data);
|
|
req->data = new uint8_t[64];
|
|
memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
|
|
*/
|
|
|
|
// This function only writes the data to the store queue, so no fault
|
|
// can happen here.
|
|
return NoFault;
|
|
}
|
|
|
|
#endif // __CPU_OZONE_LW_LSQ_HH__
|