07ea0891f1
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
36 lines
1.2 KiB
C++
36 lines
1.2 KiB
C++
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#ifndef ABSTRACTCONTROLLER_H
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#define ABSTRACTCONTROLLER_H
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/protocol/MachineType.hh"
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#include "mem/ruby/common/Address.hh"
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class MessageBuffer;
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class Network;
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class AbstractController : public Consumer {
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public:
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AbstractController() {}
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virtual void init(Network* net_ptr, const vector<string> & argv) = 0;
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// returns the number of controllers created of the specific subtype
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// virtual int getNumberOfControllers() const = 0;
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virtual MessageBuffer* getMandatoryQueue() const = 0;
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virtual const int & getVersion() const = 0;
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virtual const string toString() const = 0; // returns text version of controller type
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virtual const string getName() const = 0; // return instance name
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virtual const MachineType getMachineType() const = 0;
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virtual void blockOnQueue(Address, MessageBuffer*) = 0;
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virtual void unblock(Address) = 0;
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virtual void print(ostream & out) const = 0;
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virtual void printStats(ostream & out) const = 0;
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virtual void printConfig(ostream & out) const = 0;
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virtual void wakeup() = 0;
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// virtual void dumpStats(ostream & out) = 0;
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virtual void clearStats() = 0;
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};
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#endif
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