77b4a37067
The size of the current instruction determines what the npc should be if there's no branching.
318 lines
9.6 KiB
C++
318 lines
9.6 KiB
C++
/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_TYPES_HH__
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#define __ARCH_X86_TYPES_HH__
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#include <iostream>
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#include "arch/generic/types.hh"
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#include "base/bitunion.hh"
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#include "base/cprintf.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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#include "sim/serialize.hh"
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namespace X86ISA
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{
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//This really determines how many bytes are passed to the predecoder.
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typedef uint64_t MachInst;
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enum Prefixes {
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NoOverride,
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ESOverride,
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CSOverride,
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SSOverride,
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DSOverride,
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FSOverride,
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GSOverride,
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RexPrefix,
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OperandSizeOverride,
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AddressSizeOverride,
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Lock,
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Rep,
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Repne
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};
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BitUnion8(LegacyPrefixVector)
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Bitfield<7, 4> decodeVal;
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Bitfield<7> repne;
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Bitfield<6> rep;
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Bitfield<5> lock;
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Bitfield<4> op;
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Bitfield<3> addr;
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//There can be only one segment override, so they share the
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//first 3 bits in the legacyPrefixes bitfield.
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Bitfield<2,0> seg;
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EndBitUnion(LegacyPrefixVector)
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BitUnion8(ModRM)
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Bitfield<7,6> mod;
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Bitfield<5,3> reg;
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Bitfield<2,0> rm;
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EndBitUnion(ModRM)
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BitUnion8(Sib)
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Bitfield<7,6> scale;
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Bitfield<5,3> index;
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Bitfield<2,0> base;
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EndBitUnion(Sib)
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BitUnion8(Rex)
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//This bit doesn't mean anything according to the ISA, but in
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//this implementation, it being set means an REX prefix was present.
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Bitfield<6> present;
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Bitfield<3> w;
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Bitfield<2> r;
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Bitfield<1> x;
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Bitfield<0> b;
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EndBitUnion(Rex)
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BitUnion8(Opcode)
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Bitfield<7,3> top5;
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Bitfield<2,0> bottom3;
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EndBitUnion(Opcode)
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BitUnion8(OperatingMode)
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Bitfield<3> mode;
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Bitfield<2,0> submode;
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EndBitUnion(OperatingMode)
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enum X86Mode {
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LongMode,
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LegacyMode
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};
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enum X86SubMode {
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SixtyFourBitMode,
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CompatabilityMode,
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ProtectedMode,
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Virtual8086Mode,
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RealMode
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};
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//The intermediate structure the x86 predecoder returns.
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struct ExtMachInst
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{
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//Prefixes
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LegacyPrefixVector legacy;
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Rex rex;
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//This holds all of the bytes of the opcode
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struct
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{
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//The number of bytes in this opcode. Right now, we ignore that
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//this can be 3 in some cases
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uint8_t num;
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//The first byte detected in a 2+ byte opcode. Should be 0xF0.
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uint8_t prefixA;
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//The second byte detected in a 3+ byte opcode. Could be 0x38-0x3F
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//for some SSE instructions. 3dNow! instructions are handled as
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//two byte opcodes and then split out further by the immediate
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//byte.
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uint8_t prefixB;
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//The main opcode byte. The highest addressed byte in the opcode.
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Opcode op;
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} opcode;
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//Modifier bytes
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ModRM modRM;
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Sib sib;
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//Immediate fields
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uint64_t immediate;
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uint64_t displacement;
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//The effective operand size.
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uint8_t opSize;
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//The effective address size.
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uint8_t addrSize;
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//The effective stack size.
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uint8_t stackSize;
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//The size of the displacement
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uint8_t dispSize;
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//Mode information
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OperatingMode mode;
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};
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inline static std::ostream &
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operator << (std::ostream & os, const ExtMachInst & emi)
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{
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ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
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"op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
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"prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
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"modRM = %#x,\n\tsib = %#x,\n\t"
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"immediate = %#x,\n\tdisplacement = %#x\n\t"
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"dispSize = %d}\n",
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(uint8_t)emi.legacy, (uint8_t)emi.rex,
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emi.opcode.num, (uint8_t)emi.opcode.op,
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emi.opcode.prefixA, emi.opcode.prefixB,
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(uint8_t)emi.modRM, (uint8_t)emi.sib,
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emi.immediate, emi.displacement, emi.dispSize);
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return os;
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}
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inline static bool
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operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
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{
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if(emi1.legacy != emi2.legacy)
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return false;
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if(emi1.rex != emi2.rex)
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return false;
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if(emi1.opcode.num != emi2.opcode.num)
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return false;
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if(emi1.opcode.op != emi2.opcode.op)
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return false;
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if(emi1.opcode.prefixA != emi2.opcode.prefixA)
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return false;
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if(emi1.opcode.prefixB != emi2.opcode.prefixB)
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return false;
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if(emi1.modRM != emi2.modRM)
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return false;
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if(emi1.sib != emi2.sib)
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return false;
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if(emi1.immediate != emi2.immediate)
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return false;
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if(emi1.displacement != emi2.displacement)
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return false;
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if(emi1.mode != emi2.mode)
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return false;
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if(emi1.opSize != emi2.opSize)
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return false;
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if(emi1.addrSize != emi2.addrSize)
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return false;
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if(emi1.stackSize != emi2.stackSize)
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return false;
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if(emi1.dispSize != emi2.dispSize)
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return false;
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return true;
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}
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class PCState : public GenericISA::UPCState<MachInst>
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{
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protected:
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typedef GenericISA::UPCState<MachInst> Base;
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uint8_t _size;
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public:
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void
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set(Addr val)
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{
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Base::set(val);
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_size = 0;
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}
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PCState() {}
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PCState(Addr val) { set(val); }
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uint8_t size() const { return _size; }
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void size(uint8_t newSize) { _size = newSize; }
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bool
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branching() const
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{
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return this->npc() != this->pc() + size();
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}
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void
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advance()
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{
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Base::advance();
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_size = 0;
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}
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void
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uEnd()
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{
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Base::uEnd();
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_size = 0;
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}
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void
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serialize(std::ostream &os)
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{
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Base::serialize(os);
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SERIALIZE_SCALAR(_size);
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}
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void
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unserialize(Checkpoint *cp, const std::string §ion)
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{
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Base::unserialize(cp, section);
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UNSERIALIZE_SCALAR(_size);
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}
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};
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struct CoreSpecific {
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int core_type;
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};
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};
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namespace __hash_namespace {
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template<>
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struct hash<X86ISA::ExtMachInst> {
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size_t operator()(const X86ISA::ExtMachInst &emi) const {
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return (((uint64_t)emi.legacy << 56) |
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((uint64_t)emi.rex << 48) |
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((uint64_t)emi.modRM << 40) |
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((uint64_t)emi.sib << 32) |
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((uint64_t)emi.opcode.num << 24) |
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((uint64_t)emi.opcode.prefixA << 16) |
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((uint64_t)emi.opcode.prefixB << 8) |
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((uint64_t)emi.opcode.op)) ^
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emi.immediate ^ emi.displacement ^
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emi.mode ^
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emi.opSize ^ emi.addrSize ^
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emi.stackSize ^ emi.dispSize;
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};
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};
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}
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// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
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// and UNSERIALIZE_SCALAR.
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template <>
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void
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paramOut(std::ostream &os, const std::string &name,
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const X86ISA::ExtMachInst &machInst);
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template <>
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void
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paramIn(Checkpoint *cp, const std::string §ion,
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const std::string &name, X86ISA::ExtMachInst &machInst);
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#endif // __ARCH_X86_TYPES_HH__
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