697 lines
79 KiB
Plaintext
697 lines
79 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.555533 # Number of seconds simulated
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sim_ticks 555532734000 # Number of ticks simulated
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final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 316770 # Simulator instruction rate (inst/s)
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host_op_rate 316770 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 189468265 # Simulator tick rate (ticks/s)
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host_mem_usage 247360 # Number of bytes of host memory used
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host_seconds 2932.06 # Real time elapsed on the host
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sim_insts 928789150 # Number of instructions simulated
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sim_ops 928789150 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 18657152 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18657152 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 186688 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 186688 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 291518 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 33584253 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 33584253 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 336052 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 336052 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 7682197 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 7682197 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 7682197 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 33584253 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 41266450 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 291518 # Number of read requests accepted
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system.physmem.writeReqs 66683 # Number of write requests accepted
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system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 17088 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 267 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 17939 # Per bank write bursts
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system.physmem.perBankRdBursts::1 18284 # Per bank write bursts
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system.physmem.perBankRdBursts::2 18304 # Per bank write bursts
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system.physmem.perBankRdBursts::3 18254 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18163 # Per bank write bursts
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system.physmem.perBankRdBursts::5 18248 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18324 # Per bank write bursts
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system.physmem.perBankRdBursts::7 18299 # Per bank write bursts
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system.physmem.perBankRdBursts::8 18226 # Per bank write bursts
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system.physmem.perBankRdBursts::9 18226 # Per bank write bursts
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system.physmem.perBankRdBursts::10 18216 # Per bank write bursts
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system.physmem.perBankRdBursts::11 18389 # Per bank write bursts
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system.physmem.perBankRdBursts::12 18256 # Per bank write bursts
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system.physmem.perBankRdBursts::13 18039 # Per bank write bursts
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system.physmem.perBankRdBursts::14 17980 # Per bank write bursts
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system.physmem.perBankRdBursts::15 18104 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4190 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 555532658500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 291518 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66683 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 290760 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 981 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4046 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 105079 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 217.968119 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 139.907625 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 270.030152 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 40113 38.17% 38.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 44071 41.94% 80.11% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 8455 8.05% 88.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 717 0.68% 88.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 543 0.52% 89.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 672 0.64% 90.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1241 1.18% 91.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1153 1.10% 92.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8114 7.72% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 105079 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 71.423096 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 36.196398 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 785.521839 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.485163 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.463667 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.859123 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3065 75.79% 75.79% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 975 24.11% 99.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads
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system.physmem.totQLat 2419619750 # Total ticks spent queuing
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system.physmem.totMemAccLat 7880576000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 8307.68 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 27057.68 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 7.68 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.32 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing
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system.physmem.readRowHits 202343 # Number of row buffer hits during reads
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system.physmem.writeRowHits 50484 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 69.47 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes
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system.physmem.avgGap 1550896.45 # Average gap between requests
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system.physmem.pageHitRate 70.64 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 275459224750 # Time in different power states
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system.physmem.memoryStateTime::REF 18550220000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem.actEnergy::0 396060840 # Energy for activate commands per rank (pJ)
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system.physmem.actEnergy::1 398223000 # Energy for activate commands per rank (pJ)
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system.physmem.preEnergy::0 216104625 # Energy for precharge commands per rank (pJ)
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system.physmem.preEnergy::1 217284375 # Energy for precharge commands per rank (pJ)
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system.physmem.readEnergy::0 1136803200 # Energy for read commands per rank (pJ)
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system.physmem.readEnergy::1 1134198000 # Energy for read commands per rank (pJ)
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system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ)
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system.physmem.writeEnergy::1 215557200 # Energy for write commands per rank (pJ)
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system.physmem.refreshEnergy::0 36284230320 # Energy for refresh commands per rank (pJ)
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system.physmem.refreshEnergy::1 36284230320 # Energy for refresh commands per rank (pJ)
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system.physmem.actBackEnergy::0 106733795895 # Energy for active background per rank (pJ)
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system.physmem.actBackEnergy::1 107171521695 # Energy for active background per rank (pJ)
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system.physmem.preBackEnergy::0 239689369500 # Energy for precharge background per rank (pJ)
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system.physmem.preBackEnergy::1 239305399500 # Energy for precharge background per rank (pJ)
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system.physmem.totalEnergy::0 384672802860 # Total energy per rank (pJ)
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system.physmem.totalEnergy::1 384726414090 # Total energy per rank (pJ)
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system.physmem.averagePower::0 692.448078 # Core power per rank (mW)
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system.physmem.averagePower::1 692.544584 # Core power per rank (mW)
|
|
system.membus.trans_dist::ReadReq 224874 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 224874 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 66644 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 66644 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 358201 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 358201 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 358201 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 954482500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2723745500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 125108663 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 80505376 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 103330871 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 82874854 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 18690215 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 237537573 # DTB read hits
|
|
system.cpu.dtb.read_misses 198412 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 237735985 # DTB read accesses
|
|
system.cpu.dtb.write_hits 98305055 # DTB write hits
|
|
system.cpu.dtb.write_misses 7206 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 98312261 # DTB write accesses
|
|
system.cpu.dtb.data_hits 335842628 # DTB hits
|
|
system.cpu.dtb.data_misses 205618 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 336048246 # DTB accesses
|
|
system.cpu.itb.fetch_hits 315070347 # ITB hits
|
|
system.cpu.itb.fetch_misses 120 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 315070467 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 37 # Number of system calls
|
|
system.cpu.numCycles 1111065468 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 928789150 # Number of instructions committed
|
|
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 23870771 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.196252 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.835945 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 58517266 # Total number of cycles that the object has spent stopped
|
|
system.cpu.icache.tags.replacements 10608 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1686.446779 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 315057996 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 25510.768907 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1686.446779 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 630153044 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 630153044 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 315057996 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 315057996 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 315057996 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 315057996 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 315057996 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 315057996 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 12351 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 334498250 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 334498250 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 334498250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 334498250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 334498250 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 334498250 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 315070347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 315070347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 315070347 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 315070347 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 315070347 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 315070347 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27082.685613 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 27082.685613 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 27082.685613 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 27082.685613 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 12351 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 12351 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308545750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 308545750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308545750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 308545750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308545750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 308545750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24981.438750 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 69010 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 69010 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 884470 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 884470 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 884470 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 19151250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1221989250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.l2cache.tags.replacements 258739 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32601.629306 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 523854 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 291475 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 1.797252 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 2865.774027 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.855280 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.087456 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907466 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.994923 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2681 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29449 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 7436245 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 7436245 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 499096 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 499096 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 501462 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 501462 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 501462 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 501462 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 224875 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 66644 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66644 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 291519 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 291519 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 291519 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 291519 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15924584250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 15924584250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4349858250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4349858250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 20274442500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 20274442500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 20274442500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 20274442500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 723971 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 723971 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69010 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 69010 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 792981 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 792981 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 792981 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 792981 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.310613 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.310613 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.965715 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965715 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367624 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.367624 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70815.271818 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70815.271818 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65270.065572 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65270.065572 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69547.585235 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69547.585235 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224875 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66644 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66644 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 291519 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 291519 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 291519 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 291519 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13108086750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13108086750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3516385750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3516385750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16624472500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 16624472500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16624472500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 16624472500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310613 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310613 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965715 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965715 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.367624 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.367624 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58290.546971 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58290.546971 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52763.725917 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.725917 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 776534 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4092.879782 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 322859767 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 413.588726 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879782 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 648198336 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 648198336 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.inst 224695720 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 224695720 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.inst 322859767 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 322859767 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.inst 322859767 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 322859767 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.inst 849086 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 849086 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22831828750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 22831828750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9022635000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9022635000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.inst 31854463750 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 31854463750 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.inst 31854463750 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 31854463750 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 225407653 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 225407653 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.inst 323708853 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 323708853 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.inst 323708853 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 323708853 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32070.193052 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 32070.193052 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65785.181513 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 65785.181513 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 37516.180634 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 37516.180634 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 91489 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 313 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68143 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 68456 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 68456 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711620 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 711620 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69010 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 69010 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21330988000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21330988000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4442556750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4442556750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25773544750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 25773544750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25773544750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 25773544750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 29975.250836 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29975.250836 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64375.550645 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64375.550645 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|