c82a8979a3
The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). As observed through profiling of different protocols, multiple such lookups take place for a given cache block. It was noted that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. I have to acknowledge that the many of the thoughts that went in to this patch belong to Brad. Changes to CacheMemory, TBETable and AbstractCacheEntry classes: 1. The lookup function belonging to CacheMemory class now returns a pointer to a cache block entry, instead of a reference. The pointer is NULL in case the block being looked up is not present in the cache. Similar change has been carried out in the lookup function of the TBETable class. 2. Function for setting and getting access permission of a cache block have been moved from CacheMemory class to AbstractCacheEntry class. 3. The allocate function in CacheMemory class now returns pointer to the allocated cache entry. Changes to SLICC: 1. Each action now has implicit variables - cache_entry and tbe. cache_entry, if != NULL, must point to the cache entry for the address on which the action is being carried out. Similarly, tbe should also point to the transaction buffer entry of the address on which the action is being carried out. 2. If a cache entry or a transaction buffer entry is passed on as an argument to a function, it is presumed that a pointer is being passed on. 3. The cache entry and the tbe pointers received __implicitly__ by the actions, are passed __explicitly__ to the trigger function. 4. While performing an action, set/unset_cache_entry, set/unset_tbe are to be used for setting / unsetting cache entry and tbe pointers respectively. 5. is_valid() and is_invalid() has been made available for testing whether a given pointer 'is not NULL' and 'is NULL' respectively. 6. Local variables are now available, but they are assumed to be pointers always. 7. It is now possible for an object of the derieved class to make calls to a function defined in the interface. 8. An OOD token has been introduced in SLICC. It is same as the NULL token used in C/C++. If you are wondering, OOD stands for Out Of Domain. 9. static_cast can now taken an optional parameter that asks for casting the given variable to a pointer of the given type. 10. Functions can be annotated with 'return_by_pointer=yes' to return a pointer. 11. StateMachine has two new variables, EntryType and TBEType. EntryType is set to the type which inherits from 'AbstractCacheEntry'. There can only be one such type in the machine. TBEType is set to the type for which 'TBE' is used as the name. All the protocols have been modified to conform with the new interface.
920 lines
31 KiB
Text
920 lines
31 KiB
Text
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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machine(L1Cache, "MSI Directory L1 Cache CMP")
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: Sequencer * sequencer,
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CacheMemory * L1IcacheMemory,
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CacheMemory * L1DcacheMemory,
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int l2_select_num_bits,
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int l1_request_latency = 2,
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int l1_response_latency = 2,
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int to_l2_latency = 1
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{
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// NODE L1 CACHE
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// From this node's L1 cache TO the network
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// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
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MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
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// a local L1 -> this L2 bank
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MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false";
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MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false";
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// To this node's L1 cache FROM the network
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// a L2 bank -> this L1
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MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false";
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// a L2 bank -> this L1
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MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false";
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// STATES
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enumeration(State, desc="Cache states", default="L1Cache_State_I") {
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// Base states
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NP, desc="Not present in either cache";
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I, desc="a L1 cache entry Idle";
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S, desc="a L1 cache entry Shared";
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E, desc="a L1 cache entry Exclusive";
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M, desc="a L1 cache entry Modified", format="!b";
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// Transient States
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IS, desc="L1 idle, issued GETS, have not seen response yet";
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IM, desc="L1 idle, issued GETX, have not seen response yet";
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SM, desc="L1 idle, issued GETX, have not seen response yet";
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IS_I, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
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M_I, desc="L1 replacing, waiting for ACK";
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E_I, desc="L1 replacing, waiting for ACK";
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SINK_WB_ACK, desc="This is to sink WB_Acks from L2";
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}
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// EVENTS
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enumeration(Event, desc="Cache events") {
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// L1 events
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Load, desc="Load request from the home processor";
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Ifetch, desc="I-fetch request from the home processor";
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Store, desc="Store request from the home processor";
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Inv, desc="Invalidate request from L2 bank";
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// internal generated request
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L1_Replacement, desc="L1 Replacement", format="!r";
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// other requests
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Fwd_GETX, desc="GETX from other processor";
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Fwd_GETS, desc="GETS from other processor";
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Fwd_GET_INSTR, desc="GET_INSTR from other processor";
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Data, desc="Data for processor";
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Data_Exclusive, desc="Data for processor";
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DataS_fromL1, desc="data for GETS request, need to unblock directory";
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Data_all_Acks, desc="Data for processor, all acks";
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Ack, desc="Ack for processor";
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Ack_all, desc="Last ack for processor";
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WB_Ack, desc="Ack for replacement";
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}
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// TYPES
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
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State CacheState, desc="cache state";
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DataBlock DataBlk, desc="data for the block";
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bool Dirty, default="false", desc="data is dirty";
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}
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// TBE fields
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structure(TBE, desc="...") {
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Address Address, desc="Physical address for this TBE";
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Buffer for the data block";
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bool Dirty, default="false", desc="data is dirty";
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bool isPrefetch, desc="Set if this was caused by a prefetch";
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int pendingAcks, default="0", desc="number of pending acks";
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
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MessageBuffer mandatoryQueue, ordered="false";
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int cache_state_to_int(State state);
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int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
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void set_cache_entry(AbstractCacheEntry a);
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void unset_cache_entry();
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void set_tbe(TBE a);
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void unset_tbe();
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// inclusive cache returns L1 entries only
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Entry getCacheEntry(Address addr), return_by_pointer="yes" {
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
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if(is_valid(L1Dcache_entry)) {
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return L1Dcache_entry;
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}
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
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return L1Icache_entry;
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}
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Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
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return L1Dcache_entry;
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}
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Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
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return L1Icache_entry;
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}
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State getState(TBE tbe, Entry cache_entry, Address addr) {
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assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
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if(is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:NP;
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}
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void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
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assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
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// MUST CHANGE
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if(is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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// Set permission
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if (state == State:I) {
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cache_entry.changePermission(AccessPermission:Invalid);
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} else if (state == State:S || state == State:E) {
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cache_entry.changePermission(AccessPermission:Read_Only);
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} else if (state == State:M) {
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cache_entry.changePermission(AccessPermission:Read_Write);
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} else {
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cache_entry.changePermission(AccessPermission:Busy);
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}
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}
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}
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Event mandatory_request_type_to_event(CacheRequestType type) {
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if (type == CacheRequestType:LD) {
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return Event:Load;
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} else if (type == CacheRequestType:IFETCH) {
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return Event:Ifetch;
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} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
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return Event:Store;
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} else {
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error("Invalid CacheRequestType");
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}
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}
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int getPendingAcks(TBE tbe) {
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return tbe.pendingAcks;
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}
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out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
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out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
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out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
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// Response IntraChip L1 Network - response msg to this L1 cache
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in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache) {
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if (responseIntraChipL1Network_in.isReady()) {
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peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Address") {
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assert(in_msg.Destination.isElement(machineID));
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := L1_TBEs[in_msg.Address];
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if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
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trigger(Event:Data_Exclusive, in_msg.Address, cache_entry, tbe);
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} else if(in_msg.Type == CoherenceResponseType:DATA) {
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if ((getState(tbe, cache_entry, in_msg.Address) == State:IS ||
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getState(tbe, cache_entry, in_msg.Address) == State:IS_I) &&
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machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
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trigger(Event:DataS_fromL1, in_msg.Address, cache_entry, tbe);
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} else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
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trigger(Event:Data_all_Acks, in_msg.Address, cache_entry, tbe);
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} else {
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trigger(Event:Data, in_msg.Address, cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceResponseType:ACK) {
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if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
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trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
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} else {
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trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
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trigger(Event:WB_Ack, in_msg.Address, cache_entry, tbe);
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} else {
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error("Invalid L1 response type");
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}
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}
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}
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}
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// Request InterChip network - request from this L1 cache to the shared L2
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in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache) {
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if(requestIntraChipL1Network_in.isReady()) {
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peek(requestIntraChipL1Network_in, RequestMsg, block_on="Address") {
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assert(in_msg.Destination.isElement(machineID));
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := L1_TBEs[in_msg.Address];
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if (in_msg.Type == CoherenceRequestType:INV) {
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trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:UPGRADE) {
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// upgrade transforms to GETX due to race
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trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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trigger(Event:Fwd_GETS, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
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trigger(Event:Fwd_GET_INSTR, in_msg.Address, cache_entry, tbe);
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} else {
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error("Invalid forwarded request type");
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}
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}
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}
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}
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// Mandatory Queue betweens Node's CPU and it's L1 caches
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in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady()) {
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peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
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// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
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if (in_msg.Type == CacheRequestType:IFETCH) {
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// ** INSTRUCTION ACCESS ***
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// Check to see if it is in the OTHER L1
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Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
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if (is_valid(L1Dcache_entry)) {
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// The block is in the wrong L1, put the request on the queue to the shared L2
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trigger(Event:L1_Replacement, in_msg.LineAddress,
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L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
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}
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Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
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if (is_valid(L1Icache_entry)) {
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// The tag matches for the L1, so the L1 asks the L2 for it.
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
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L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
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} else {
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if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
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L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
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} else {
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// No room in the L1, so we need to make room in the L1
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trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.LineAddress),
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getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
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}
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}
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} else {
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// *** DATA ACCESS ***
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// Check to see if it is in the OTHER L1
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Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
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if (is_valid(L1Icache_entry)) {
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// The block is in the wrong L1, put the request on the queue to the shared L2
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trigger(Event:L1_Replacement, in_msg.LineAddress,
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L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
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}
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Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
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if (is_valid(L1Dcache_entry)) {
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// The tag matches for the L1, so the L1 ask the L2 for it
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
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L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
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} else {
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if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
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L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
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} else {
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// No room in the L1, so we need to make room in the L1
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trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.LineAddress),
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getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
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}
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}
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}
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}
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}
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}
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// ACTIONS
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action(a_issueGETS, "a", desc="Issue GETS") {
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peek(mandatoryQueue_in, CacheMsg) {
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enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETS;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Prefetch := in_msg.Prefetch;
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out_msg.AccessMode := in_msg.AccessMode;
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}
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}
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}
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action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
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peek(mandatoryQueue_in, CacheMsg) {
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enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GET_INSTR;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Prefetch := in_msg.Prefetch;
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out_msg.AccessMode := in_msg.AccessMode;
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}
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}
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}
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action(b_issueGETX, "b", desc="Issue GETX") {
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peek(mandatoryQueue_in, CacheMsg) {
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enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETX;
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out_msg.Requestor := machineID;
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DPRINTF(RubySlicc, "%s\n", machineID);
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Prefetch := in_msg.Prefetch;
|
|
out_msg.AccessMode := in_msg.AccessMode;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(c_issueUPGRADE, "c", desc="Issue GETX") {
|
|
peek(mandatoryQueue_in, CacheMsg) {
|
|
enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:UPGRADE;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
|
|
address, out_msg.Destination);
|
|
out_msg.MessageSize := MessageSizeType:Control;
|
|
out_msg.Prefetch := in_msg.Prefetch;
|
|
out_msg.AccessMode := in_msg.AccessMode;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(d_sendDataToRequestor, "d", desc="send data to requestor") {
|
|
peek(requestIntraChipL1Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
|
|
peek(requestIntraChipL1Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
|
|
action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
|
|
peek(requestIntraChipL1Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:ACK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
}
|
|
}
|
|
|
|
action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
}
|
|
}
|
|
|
|
action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
|
|
peek(requestIntraChipL1Network_in, RequestMsg) {
|
|
enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:ACK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
out_msg.AckCount := 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
action(g_issuePUTX, "g", desc="send data to the L2 cache") {
|
|
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:PUTX;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.Requestor:= machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
if (cache_entry.Dirty) {
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
} else {
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:UNBLOCK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
DPRINTF(RubySlicc, "%s\n", address);
|
|
|
|
}
|
|
}
|
|
|
|
action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
|
l2_select_low_bit, l2_select_num_bits));
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
DPRINTF(RubySlicc, "%s\n", address);
|
|
|
|
}
|
|
}
|
|
|
|
action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
sequencer.readCallback(address, cache_entry.DataBlk);
|
|
}
|
|
|
|
action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
sequencer.writeCallback(address, cache_entry.DataBlk);
|
|
cache_entry.Dirty := true;
|
|
}
|
|
|
|
action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
|
|
check_allocate(L1_TBEs);
|
|
assert(is_valid(cache_entry));
|
|
L1_TBEs.allocate(address);
|
|
set_tbe(L1_TBEs[address]);
|
|
tbe.isPrefetch := false;
|
|
tbe.Dirty := cache_entry.Dirty;
|
|
tbe.DataBlk := cache_entry.DataBlk;
|
|
}
|
|
|
|
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
|
|
mandatoryQueue_in.dequeue();
|
|
}
|
|
|
|
action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") {
|
|
profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles());
|
|
}
|
|
|
|
action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") {
|
|
profileMsgDelay(3, responseIntraChipL1Network_in.dequeue_getDelayCycles());
|
|
}
|
|
|
|
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
|
|
L1_TBEs.deallocate(address);
|
|
unset_tbe();
|
|
}
|
|
|
|
action(u_writeDataToL1Cache, "u", desc="Write data to cache") {
|
|
peek(responseIntraChipL1Network_in, ResponseMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
cache_entry.Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(q_updateAckCount, "q", desc="Update ack count") {
|
|
peek(responseIntraChipL1Network_in, ResponseMsg) {
|
|
assert(is_valid(tbe));
|
|
tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
|
|
APPEND_TRANSITION_COMMENT(in_msg.AckCount);
|
|
APPEND_TRANSITION_COMMENT(" p: ");
|
|
APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
|
|
}
|
|
}
|
|
|
|
action(z_stall, "z", desc="Stall") {
|
|
}
|
|
|
|
action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
|
|
if (L1DcacheMemory.isTagPresent(address)) {
|
|
L1DcacheMemory.deallocate(address);
|
|
} else {
|
|
L1IcacheMemory.deallocate(address);
|
|
}
|
|
unset_cache_entry();
|
|
}
|
|
|
|
action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(zz_recycleRequestQueue, "zz", desc="recycle L1 request queue") {
|
|
requestIntraChipL1Network_in.recycle();
|
|
}
|
|
|
|
action(z_recycleMandatoryQueue, "\z", desc="recycle L1 request queue") {
|
|
mandatoryQueue_in.recycle();
|
|
}
|
|
|
|
|
|
//*****************************************************
|
|
// TRANSITIONS
|
|
//*****************************************************
|
|
|
|
// Transitions for Load/Store/Replacement/WriteBack from transient states
|
|
transition({IS, IM, IS_I, M_I, E_I, SM}, {Load, Ifetch, Store, L1_Replacement}) {
|
|
z_recycleMandatoryQueue;
|
|
}
|
|
|
|
// Transitions from Idle
|
|
transition({NP,I}, L1_Replacement) {
|
|
ff_deallocateL1CacheBlock;
|
|
}
|
|
|
|
transition({NP,I}, Load, IS) {
|
|
oo_allocateL1DCacheBlock;
|
|
i_allocateTBE;
|
|
a_issueGETS;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({NP,I}, Ifetch, IS) {
|
|
pp_allocateL1ICacheBlock;
|
|
i_allocateTBE;
|
|
ai_issueGETINSTR;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({NP,I}, Store, IM) {
|
|
oo_allocateL1DCacheBlock;
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({NP, I}, Inv) {
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
// Transitions from Shared
|
|
transition(S, {Load,Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(S, Store, SM) {
|
|
i_allocateTBE;
|
|
c_issueUPGRADE;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(S, L1_Replacement, I) {
|
|
ff_deallocateL1CacheBlock;
|
|
}
|
|
|
|
transition(S, Inv, I) {
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
// Transitions from Exclusive
|
|
|
|
transition(E, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(E, Store, M) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(E, L1_Replacement, M_I) {
|
|
// silent E replacement??
|
|
i_allocateTBE;
|
|
g_issuePUTX; // send data, but hold in case forwarded request
|
|
ff_deallocateL1CacheBlock;
|
|
}
|
|
|
|
transition(E, Inv, I) {
|
|
// don't send data
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(E, Fwd_GETX, I) {
|
|
d_sendDataToRequestor;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
|
|
d_sendDataToRequestor;
|
|
d2_sendDataToL2;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
// Transitions from Modified
|
|
transition(M, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(M, Store) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(M, L1_Replacement, M_I) {
|
|
i_allocateTBE;
|
|
g_issuePUTX; // send data, but hold in case forwarded request
|
|
ff_deallocateL1CacheBlock;
|
|
}
|
|
|
|
transition(M_I, WB_Ack, I) {
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(M, Inv, I) {
|
|
f_sendDataToL2;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(M_I, Inv, SINK_WB_ACK) {
|
|
ft_sendDataToL2_fromTBE;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(M, Fwd_GETX, I) {
|
|
d_sendDataToRequestor;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
|
|
d_sendDataToRequestor;
|
|
d2_sendDataToL2;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(M_I, Fwd_GETX, SINK_WB_ACK) {
|
|
dt_sendDataToRequestor_fromTBE;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(M_I, {Fwd_GETS, Fwd_GET_INSTR}, SINK_WB_ACK) {
|
|
dt_sendDataToRequestor_fromTBE;
|
|
d2t_sendDataToL2_fromTBE;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
// Transitions from IS
|
|
transition({IS, IS_I}, Inv, IS_I) {
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(IS, Data_all_Acks, S) {
|
|
u_writeDataToL1Cache;
|
|
h_load_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(IS_I, Data_all_Acks, I) {
|
|
u_writeDataToL1Cache;
|
|
h_load_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
|
|
transition(IS, DataS_fromL1, S) {
|
|
u_writeDataToL1Cache;
|
|
j_sendUnblock;
|
|
h_load_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(IS_I, DataS_fromL1, I) {
|
|
u_writeDataToL1Cache;
|
|
j_sendUnblock;
|
|
h_load_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
// directory is blocked when sending exclusive data
|
|
transition(IS_I, Data_Exclusive, E) {
|
|
u_writeDataToL1Cache;
|
|
h_load_hit;
|
|
jj_sendExclusiveUnblock;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(IS, Data_Exclusive, E) {
|
|
u_writeDataToL1Cache;
|
|
h_load_hit;
|
|
jj_sendExclusiveUnblock;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
// Transitions from IM
|
|
transition({IM, SM}, Inv, IM) {
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(IM, Data, SM) {
|
|
u_writeDataToL1Cache;
|
|
q_updateAckCount;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(IM, Data_all_Acks, M) {
|
|
u_writeDataToL1Cache;
|
|
hh_store_hit;
|
|
jj_sendExclusiveUnblock;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
// transitions from SM
|
|
transition({SM, IM}, Ack) {
|
|
q_updateAckCount;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(SM, Ack_all, M) {
|
|
jj_sendExclusiveUnblock;
|
|
hh_store_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(SINK_WB_ACK, {Load, Store, Ifetch, L1_Replacement}){
|
|
z_recycleMandatoryQueue;
|
|
|
|
}
|
|
|
|
transition(SINK_WB_ACK, Inv){
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(SINK_WB_ACK, WB_Ack){
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
}
|
|
}
|
|
|
|
|
|
|