5b08e211ab
Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
919 lines
104 KiB
Text
919 lines
104 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000022 # Number of seconds simulated
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sim_ticks 21842500 # Number of ticks simulated
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final_tick 21842500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 54203 # Simulator instruction rate (inst/s)
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host_op_rate 54195 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 229554116 # Simulator tick rate (ticks/s)
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host_mem_usage 222444 # Number of bytes of host memory used
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host_seconds 0.10 # Real time elapsed on the host
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sim_insts 5156 # Number of instructions simulated
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sim_ops 5156 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30464 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 476 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 981572622 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 413139522 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1394712144 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 981572622 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 981572622 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 981572622 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 413139522 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1394712144 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 476 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 476 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 30464 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 30464 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 30 # Per bank write bursts
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system.physmem.perBankRdBursts::1 0 # Per bank write bursts
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system.physmem.perBankRdBursts::2 1 # Per bank write bursts
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system.physmem.perBankRdBursts::3 0 # Per bank write bursts
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system.physmem.perBankRdBursts::4 7 # Per bank write bursts
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system.physmem.perBankRdBursts::5 3 # Per bank write bursts
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system.physmem.perBankRdBursts::6 13 # Per bank write bursts
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system.physmem.perBankRdBursts::7 54 # Per bank write bursts
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system.physmem.perBankRdBursts::8 63 # Per bank write bursts
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system.physmem.perBankRdBursts::9 77 # Per bank write bursts
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system.physmem.perBankRdBursts::10 44 # Per bank write bursts
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system.physmem.perBankRdBursts::11 20 # Per bank write bursts
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system.physmem.perBankRdBursts::12 51 # Per bank write bursts
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system.physmem.perBankRdBursts::13 29 # Per bank write bursts
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system.physmem.perBankRdBursts::14 77 # Per bank write bursts
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system.physmem.perBankRdBursts::15 7 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 21770000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 476 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 108 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 255.407407 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 175.497802 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 250.634672 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 31 28.70% 28.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 39 36.11% 64.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 16 14.81% 79.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 8 7.41% 87.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 4 3.70% 90.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1 0.93% 91.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 3 2.78% 94.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1 0.93% 95.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 5 4.63% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 108 # Bytes accessed per row activation
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system.physmem.totQLat 4718000 # Total ticks spent queuing
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system.physmem.totMemAccLat 13643000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2380000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 9911.76 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28661.76 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1394.71 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1394.71 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 10.90 # Data bus utilization in percentage
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system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 358 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 75.21 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 45735.29 # Average gap between requests
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system.physmem.pageHitRate 75.21 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
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system.physmem.memoryStateTime::REF 520000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 15316000 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.throughput 1394712144 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 425 # Transaction distribution
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system.membus.trans_dist::ReadResp 425 # Transaction distribution
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system.membus.trans_dist::ReadExReq 51 # Transaction distribution
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system.membus.trans_dist::ReadExResp 51 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 952 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 952 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30464 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 30464 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 30464 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
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system.membus.respLayer1.occupancy 4464750 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 2178 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1497 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 491 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 29.596142 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
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|
system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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|
system.cpu.itb.read_misses 0 # DTB read misses
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|
system.cpu.itb.read_accesses 0 # DTB read accesses
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|
system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
|
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system.cpu.itb.write_accesses 0 # DTB write accesses
|
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 8 # Number of system calls
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system.cpu.numCycles 43686 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 8839 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 13190 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2178 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 749 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 3214 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1378 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 1314 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 14424 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.914448 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.226738 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 11210 77.72% 77.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1316 9.12% 86.84% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 106 0.73% 87.58% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 131 0.91% 88.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 113 0.78% 91.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 150 1.04% 92.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 160 1.11% 93.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 933 6.47% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 14424 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.049856 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.301927 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 8852 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 1624 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 3059 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 872 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 12284 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 872 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 9006 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 365 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 2923 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 285 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 11879 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.SQFullEvents 266 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 14112 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 13884 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 151 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 9223 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 8300 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 3436 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 2075 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 14424 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.575430 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.252383 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 10895 75.53% 75.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 1375 9.53% 85.07% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 844 5.85% 90.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 571 3.96% 94.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 375 2.60% 97.48% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 225 1.56% 99.04% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 91 0.63% 99.67% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 14424 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 5 3.09% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 102 62.96% 66.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 55 33.95% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 4936 59.47% 59.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.58% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2249 27.10% 86.67% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1106 13.33% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 8300 # Type of FU issued
|
|
system.cpu.iq.rate 0.189992 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 162 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.019518 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 31229 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 12679 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 8460 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1305 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 270 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 872 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 287 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 10750 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 365 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 7921 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 379 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1515 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3187 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1350 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1077 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.181317 # Inst execution rate
|
|
system.cpu.iew.wb_sent 7554 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 7469 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 2985 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 4341 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.170970 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.687630 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 4930 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 13552 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.428940 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.213640 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 11200 82.64% 82.64% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 943 6.96% 89.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 594 4.38% 93.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 344 2.54% 96.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 162 1.20% 97.72% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 97 0.72% 98.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 69 0.51% 98.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 41 0.30% 99.25% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 13552 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5813 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2088 # Number of memory references committed
|
|
system.cpu.commit.loads 1163 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 915 # Number of branches committed
|
|
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 87 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 5813 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 24180 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 22370 # The number of ROB writes
|
|
system.cpu.timesIdled 295 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 29262 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5156 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 8.472847 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 8.472847 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.118024 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.118024 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 10764 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 5241 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 148 # number of misc regfile reads
|
|
system.cpu.toL2Bus.throughput 1403502346 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 428 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 958 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 30656 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 571750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 226500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 17 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 161.396825 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 1520 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 4.497041 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 161.396825 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.078807 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.078807 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 4280 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 4280 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1520 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1520 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1520 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1520 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1520 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1520 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 451 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31166000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 31166000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 31166000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 31166000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 31166000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 31166000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228818 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.228818 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.228818 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.228818 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.228818 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.228818 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69104.212860 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 69104.212860 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 69104.212860 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 69104.212860 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24162750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 24162750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24162750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 24162750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24162750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 24162750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.171487 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.171487 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.171487 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71487.426036 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71487.426036 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 221.498533 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 425 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.007059 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.688333 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810199 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 425 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012970 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 4308 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 4308 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 476 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23794750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6985750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 30780500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 23794750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10762000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 34556750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 23794750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10762000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 34556750 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71029.104478 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77619.444444 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72424.705882 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72598.214286 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72598.214286 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19559250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5880750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25440000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19559250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9025000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 28584250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19559250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9025000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 28584250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58385.820896 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65341.666667 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59858.823529 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58385.820896 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64007.092199 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60050.945378 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58385.820896 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64007.092199 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60050.945378 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 91.608220 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 91.608220 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.022365 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.022365 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 5965 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 5965 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2400 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 150 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 150 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 512 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10436500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 10436500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22532249 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 22532249 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 32968749 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 32968749 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 32968749 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 32968749 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1987 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1987 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2912 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2912 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2912 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2912 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075491 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.075491 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.175824 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.175824 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.175824 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.175824 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69576.666667 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 69576.666667 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62243.781768 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 62243.781768 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 64392.087891 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 64392.087891 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7079250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7079250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10907499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10907499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10907499 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10907499 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045294 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045294 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.048420 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.048420 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78658.333333 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78658.333333 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|