Ali Saidi 06a9f58c68 DMA: Add IOCache and fix bus bridge to optionally only send requests one ... way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964		2007-08-10 16:14:01 -04:00
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miss	cache/memtest: fixes for functional accesses.	2007-07-27 12:46:45 -07:00
prefetch	Getting closer...	2007-06-21 11:59:17 -07:00
tags	Merge python and x86 changes with cache branch	2007-07-26 23:15:49 -07:00
base_cache.cc	DMA: Add IOCache and fix bus bridge to optionally only send requests one	2007-08-10 16:14:01 -04:00
base_cache.hh	DMA: Add IOCache and fix bus bridge to optionally only send requests one	2007-08-10 16:14:01 -04:00
BaseCache.py	DMA: Add IOCache and fix bus bridge to optionally only send requests one	2007-08-10 16:14:01 -04:00
cache.cc	Get rid of coherence protocol object.	2007-06-27 20:54:13 -07:00
cache.hh	DMA: Add IOCache and fix bus bridge to optionally only send requests one	2007-08-10 16:14:01 -04:00
cache_blk.hh	More major reorg of cache. Seems to work for atomic mode now,	2007-06-17 17:27:53 -07:00
cache_builder.cc	DMA: Add IOCache and fix bus bridge to optionally only send requests one	2007-08-10 16:14:01 -04:00
cache_impl.hh	DMA: Add IOCache and fix bus bridge to optionally only send requests one	2007-08-10 16:14:01 -04:00
SConscript	Move SimObject python files alongside the C++ and fix	2007-05-27 19:21:17 -07:00