0622f30961
This patch adds a predecessor field to the SenderState base class to make the process of linking them up more uniform, and enable a traversal of the stack without knowing the specific type of the subclasses. There are a number of simplifications done as part of changing the SenderState, particularly in the RubyTest.
733 lines
25 KiB
C++
733 lines
25 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/misc.hh"
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#include "base/str.hh"
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#include "config/the_isa.hh"
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#if THE_ISA == X86_ISA
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#include "arch/x86/insts/microldstop.hh"
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#endif // X86_ISA
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#include "cpu/testers/rubytest/RubyTester.hh"
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#include "debug/MemoryAccess.hh"
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#include "debug/ProtocolTrace.hh"
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#include "debug/RubySequencer.hh"
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#include "debug/RubyStats.hh"
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#include "mem/protocol/PrefetchBit.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/slicc_interface/RubyRequest.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "mem/ruby/system/System.hh"
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#include "mem/packet.hh"
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using namespace std;
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Sequencer *
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RubySequencerParams::create()
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{
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return new Sequencer(this);
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}
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Sequencer::Sequencer(const Params *p)
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: RubyPort(p), deadlockCheckEvent(this)
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{
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m_store_waiting_on_load_cycles = 0;
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m_store_waiting_on_store_cycles = 0;
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m_load_waiting_on_store_cycles = 0;
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m_load_waiting_on_load_cycles = 0;
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m_outstanding_count = 0;
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m_instCache_ptr = p->icache;
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m_dataCache_ptr = p->dcache;
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m_max_outstanding_requests = p->max_outstanding_requests;
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m_deadlock_threshold = p->deadlock_threshold;
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assert(m_max_outstanding_requests > 0);
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assert(m_deadlock_threshold > 0);
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assert(m_instCache_ptr != NULL);
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assert(m_dataCache_ptr != NULL);
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m_usingNetworkTester = p->using_network_tester;
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}
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Sequencer::~Sequencer()
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{
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}
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void
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Sequencer::wakeup()
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{
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assert(getDrainState() != Drainable::Draining);
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// Check for deadlock of any of the requests
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Cycles current_time = curCycle();
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// Check across all outstanding requests
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int total_outstanding = 0;
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RequestTable::iterator read = m_readRequestTable.begin();
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RequestTable::iterator read_end = m_readRequestTable.end();
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for (; read != read_end; ++read) {
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SequencerRequest* request = read->second;
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if (current_time - request->issue_time < m_deadlock_threshold)
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continue;
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panic("Possible Deadlock detected. Aborting!\n"
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"version: %d request.paddr: 0x%x m_readRequestTable: %d "
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"current time: %u issue_time: %d difference: %d\n", m_version,
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Address(request->pkt->getAddr()), m_readRequestTable.size(),
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current_time * clockPeriod(), request->issue_time * clockPeriod(),
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(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
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}
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RequestTable::iterator write = m_writeRequestTable.begin();
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RequestTable::iterator write_end = m_writeRequestTable.end();
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for (; write != write_end; ++write) {
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SequencerRequest* request = write->second;
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if (current_time - request->issue_time < m_deadlock_threshold)
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continue;
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panic("Possible Deadlock detected. Aborting!\n"
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"version: %d request.paddr: 0x%x m_writeRequestTable: %d "
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"current time: %u issue_time: %d difference: %d\n", m_version,
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Address(request->pkt->getAddr()), m_writeRequestTable.size(),
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current_time * clockPeriod(), request->issue_time * clockPeriod(),
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(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
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}
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total_outstanding += m_writeRequestTable.size();
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total_outstanding += m_readRequestTable.size();
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assert(m_outstanding_count == total_outstanding);
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if (m_outstanding_count > 0) {
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// If there are still outstanding requests, keep checking
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schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
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}
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}
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void
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Sequencer::printStats(ostream & out) const
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{
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out << "Sequencer: " << m_name << endl
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<< " store_waiting_on_load_cycles: "
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<< m_store_waiting_on_load_cycles << endl
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<< " store_waiting_on_store_cycles: "
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<< m_store_waiting_on_store_cycles << endl
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<< " load_waiting_on_load_cycles: "
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<< m_load_waiting_on_load_cycles << endl
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<< " load_waiting_on_store_cycles: "
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<< m_load_waiting_on_store_cycles << endl;
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}
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void
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Sequencer::printProgress(ostream& out) const
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{
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#if 0
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int total_demand = 0;
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out << "Sequencer Stats Version " << m_version << endl;
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out << "Current time = " << g_system_ptr->getTime() << endl;
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out << "---------------" << endl;
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out << "outstanding requests" << endl;
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out << "proc " << m_Read
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<< " version Requests = " << m_readRequestTable.size() << endl;
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// print the request table
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RequestTable::iterator read = m_readRequestTable.begin();
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RequestTable::iterator read_end = m_readRequestTable.end();
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for (; read != read_end; ++read) {
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SequencerRequest* request = read->second;
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out << "\tRequest[ " << i << " ] = " << request->type
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<< " Address " << rkeys[i]
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<< " Posted " << request->issue_time
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<< " PF " << PrefetchBit_No << endl;
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total_demand++;
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}
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out << "proc " << m_version
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<< " Write Requests = " << m_writeRequestTable.size << endl;
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// print the request table
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RequestTable::iterator write = m_writeRequestTable.begin();
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RequestTable::iterator write_end = m_writeRequestTable.end();
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for (; write != write_end; ++write) {
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SequencerRequest* request = write->second;
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out << "\tRequest[ " << i << " ] = " << request.getType()
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<< " Address " << wkeys[i]
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<< " Posted " << request.getTime()
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<< " PF " << request.getPrefetch() << endl;
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if (request.getPrefetch() == PrefetchBit_No) {
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total_demand++;
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}
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}
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out << endl;
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out << "Total Number Outstanding: " << m_outstanding_count << endl
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<< "Total Number Demand : " << total_demand << endl
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<< "Total Number Prefetches : " << m_outstanding_count - total_demand
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<< endl << endl << endl;
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#endif
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}
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// Insert the request on the correct request table. Return true if
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// the entry was already present.
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RequestStatus
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Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
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{
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assert(m_outstanding_count ==
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(m_writeRequestTable.size() + m_readRequestTable.size()));
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// See if we should schedule a deadlock check
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if (!deadlockCheckEvent.scheduled() &&
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getDrainState() != Drainable::Draining) {
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schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
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}
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Address line_addr(pkt->getAddr());
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line_addr.makeLineAddress();
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// Create a default entry, mapping the address to NULL, the cast is
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// there to make gcc 4.4 happy
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RequestTable::value_type default_entry(line_addr,
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(SequencerRequest*) NULL);
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if ((request_type == RubyRequestType_ST) ||
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(request_type == RubyRequestType_RMW_Read) ||
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(request_type == RubyRequestType_RMW_Write) ||
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(request_type == RubyRequestType_Load_Linked) ||
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(request_type == RubyRequestType_Store_Conditional) ||
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(request_type == RubyRequestType_Locked_RMW_Read) ||
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(request_type == RubyRequestType_Locked_RMW_Write) ||
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(request_type == RubyRequestType_FLUSH)) {
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// Check if there is any outstanding read request for the same
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// cache line.
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if (m_readRequestTable.count(line_addr) > 0) {
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m_store_waiting_on_load_cycles++;
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return RequestStatus_Aliased;
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}
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pair<RequestTable::iterator, bool> r =
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m_writeRequestTable.insert(default_entry);
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if (r.second) {
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RequestTable::iterator i = r.first;
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i->second = new SequencerRequest(pkt, request_type, curCycle());
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m_outstanding_count++;
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} else {
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// There is an outstanding write request for the cache line
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m_store_waiting_on_store_cycles++;
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return RequestStatus_Aliased;
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}
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} else {
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// Check if there is any outstanding write request for the same
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// cache line.
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if (m_writeRequestTable.count(line_addr) > 0) {
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m_load_waiting_on_store_cycles++;
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return RequestStatus_Aliased;
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}
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pair<RequestTable::iterator, bool> r =
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m_readRequestTable.insert(default_entry);
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if (r.second) {
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RequestTable::iterator i = r.first;
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i->second = new SequencerRequest(pkt, request_type, curCycle());
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m_outstanding_count++;
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} else {
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// There is an outstanding read request for the cache line
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m_load_waiting_on_load_cycles++;
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return RequestStatus_Aliased;
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}
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}
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g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
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assert(m_outstanding_count ==
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(m_writeRequestTable.size() + m_readRequestTable.size()));
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return RequestStatus_Ready;
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}
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void
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Sequencer::markRemoved()
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{
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m_outstanding_count--;
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assert(m_outstanding_count ==
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m_writeRequestTable.size() + m_readRequestTable.size());
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}
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void
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Sequencer::removeRequest(SequencerRequest* srequest)
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{
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assert(m_outstanding_count ==
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m_writeRequestTable.size() + m_readRequestTable.size());
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Address line_addr(srequest->pkt->getAddr());
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line_addr.makeLineAddress();
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if ((srequest->m_type == RubyRequestType_ST) ||
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(srequest->m_type == RubyRequestType_RMW_Read) ||
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(srequest->m_type == RubyRequestType_RMW_Write) ||
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(srequest->m_type == RubyRequestType_Load_Linked) ||
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(srequest->m_type == RubyRequestType_Store_Conditional) ||
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(srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
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(srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
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m_writeRequestTable.erase(line_addr);
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} else {
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m_readRequestTable.erase(line_addr);
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}
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markRemoved();
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}
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bool
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Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
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{
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//
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// The success flag indicates whether the LLSC operation was successful.
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// LL ops will always succeed, but SC may fail if the cache line is no
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// longer locked.
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//
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bool success = true;
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if (request->m_type == RubyRequestType_Store_Conditional) {
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if (!m_dataCache_ptr->isLocked(address, m_version)) {
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//
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// For failed SC requests, indicate the failure to the cpu by
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// setting the extra data to zero.
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//
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request->pkt->req->setExtraData(0);
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success = false;
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} else {
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//
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// For successful SC requests, indicate the success to the cpu by
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// setting the extra data to one.
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//
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request->pkt->req->setExtraData(1);
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}
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//
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// Independent of success, all SC operations must clear the lock
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//
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m_dataCache_ptr->clearLocked(address);
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} else if (request->m_type == RubyRequestType_Load_Linked) {
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//
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// Note: To fully follow Alpha LLSC semantics, should the LL clear any
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// previously locked cache lines?
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//
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m_dataCache_ptr->setLocked(address, m_version);
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} else if ((m_dataCache_ptr->isTagPresent(address)) &&
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(m_dataCache_ptr->isLocked(address, m_version))) {
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//
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// Normal writes should clear the locked address
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//
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m_dataCache_ptr->clearLocked(address);
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}
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return success;
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}
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void
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Sequencer::writeCallback(const Address& address, DataBlock& data)
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{
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writeCallback(address, GenericMachineType_NULL, data);
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}
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void
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Sequencer::writeCallback(const Address& address,
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GenericMachineType mach,
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DataBlock& data)
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{
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writeCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
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}
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void
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Sequencer::writeCallback(const Address& address,
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GenericMachineType mach,
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DataBlock& data,
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Cycles initialRequestTime,
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Cycles forwardRequestTime,
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Cycles firstResponseTime)
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{
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assert(address == line_address(address));
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assert(m_writeRequestTable.count(line_address(address)));
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RequestTable::iterator i = m_writeRequestTable.find(address);
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assert(i != m_writeRequestTable.end());
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SequencerRequest* request = i->second;
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m_writeRequestTable.erase(i);
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markRemoved();
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assert((request->m_type == RubyRequestType_ST) ||
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(request->m_type == RubyRequestType_ATOMIC) ||
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(request->m_type == RubyRequestType_RMW_Read) ||
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(request->m_type == RubyRequestType_RMW_Write) ||
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(request->m_type == RubyRequestType_Load_Linked) ||
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(request->m_type == RubyRequestType_Store_Conditional) ||
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(request->m_type == RubyRequestType_Locked_RMW_Read) ||
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(request->m_type == RubyRequestType_Locked_RMW_Write) ||
|
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(request->m_type == RubyRequestType_FLUSH));
|
|
|
|
|
|
//
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// For Alpha, properly handle LL, SC, and write requests with respect to
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// locked cache blocks.
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//
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// Not valid for Network_test protocl
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//
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bool success = true;
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if(!m_usingNetworkTester)
|
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success = handleLlsc(address, request);
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|
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if (request->m_type == RubyRequestType_Locked_RMW_Read) {
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m_controller->blockOnQueue(address, m_mandatory_q_ptr);
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} else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
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m_controller->unblock(address);
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}
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hitCallback(request, mach, data, success,
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initialRequestTime, forwardRequestTime, firstResponseTime);
|
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}
|
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|
|
void
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Sequencer::readCallback(const Address& address, DataBlock& data)
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{
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readCallback(address, GenericMachineType_NULL, data);
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}
|
|
|
|
void
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|
Sequencer::readCallback(const Address& address,
|
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GenericMachineType mach,
|
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DataBlock& data)
|
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{
|
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readCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
|
|
}
|
|
|
|
void
|
|
Sequencer::readCallback(const Address& address,
|
|
GenericMachineType mach,
|
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DataBlock& data,
|
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Cycles initialRequestTime,
|
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Cycles forwardRequestTime,
|
|
Cycles firstResponseTime)
|
|
{
|
|
assert(address == line_address(address));
|
|
assert(m_readRequestTable.count(line_address(address)));
|
|
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|
RequestTable::iterator i = m_readRequestTable.find(address);
|
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assert(i != m_readRequestTable.end());
|
|
SequencerRequest* request = i->second;
|
|
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m_readRequestTable.erase(i);
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markRemoved();
|
|
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|
assert((request->m_type == RubyRequestType_LD) ||
|
|
(request->m_type == RubyRequestType_IFETCH));
|
|
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|
hitCallback(request, mach, data, true,
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initialRequestTime, forwardRequestTime, firstResponseTime);
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}
|
|
|
|
void
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|
Sequencer::hitCallback(SequencerRequest* srequest,
|
|
GenericMachineType mach,
|
|
DataBlock& data,
|
|
bool success,
|
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Cycles initialRequestTime,
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|
Cycles forwardRequestTime,
|
|
Cycles firstResponseTime)
|
|
{
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PacketPtr pkt = srequest->pkt;
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Address request_address(pkt->getAddr());
|
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Address request_line_address(pkt->getAddr());
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request_line_address.makeLineAddress();
|
|
RubyRequestType type = srequest->m_type;
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Cycles issued_time = srequest->issue_time;
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// Set this cache entry to the most recently used
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if (type == RubyRequestType_IFETCH) {
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m_instCache_ptr->setMRU(request_line_address);
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} else {
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m_dataCache_ptr->setMRU(request_line_address);
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}
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|
|
|
assert(curCycle() >= issued_time);
|
|
Cycles miss_latency = curCycle() - issued_time;
|
|
|
|
// Profile the miss latency for all non-zero demand misses
|
|
if (miss_latency != 0) {
|
|
g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
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|
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|
if (mach == GenericMachineType_L1Cache_wCC) {
|
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g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
|
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initialRequestTime, forwardRequestTime,
|
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firstResponseTime, curCycle());
|
|
}
|
|
|
|
if (mach == GenericMachineType_Directory) {
|
|
g_system_ptr->getProfiler()->missLatencyDir(issued_time,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime, curCycle());
|
|
}
|
|
|
|
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
|
|
curTick(), m_version, "Seq",
|
|
success ? "Done" : "SC_Failed", "", "",
|
|
request_address, miss_latency);
|
|
}
|
|
|
|
// update the data
|
|
if (g_system_ptr->m_warmup_enabled) {
|
|
assert(pkt->getPtr<uint8_t>(false) != NULL);
|
|
data.setData(pkt->getPtr<uint8_t>(false),
|
|
request_address.getOffset(), pkt->getSize());
|
|
} else if (pkt->getPtr<uint8_t>(true) != NULL) {
|
|
if ((type == RubyRequestType_LD) ||
|
|
(type == RubyRequestType_IFETCH) ||
|
|
(type == RubyRequestType_RMW_Read) ||
|
|
(type == RubyRequestType_Locked_RMW_Read) ||
|
|
(type == RubyRequestType_Load_Linked)) {
|
|
memcpy(pkt->getPtr<uint8_t>(true),
|
|
data.getData(request_address.getOffset(), pkt->getSize()),
|
|
pkt->getSize());
|
|
} else {
|
|
data.setData(pkt->getPtr<uint8_t>(true),
|
|
request_address.getOffset(), pkt->getSize());
|
|
}
|
|
} else {
|
|
DPRINTF(MemoryAccess,
|
|
"WARNING. Data not transfered from Ruby to M5 for type %s\n",
|
|
RubyRequestType_to_string(type));
|
|
}
|
|
|
|
// If using the RubyTester, update the RubyTester sender state's
|
|
// subBlock with the recieved data. The tester will later access
|
|
// this state.
|
|
// Note: RubyPort will access it's sender state before the
|
|
// RubyTester.
|
|
if (m_usingRubyTester) {
|
|
RubyPort::SenderState *reqSenderState =
|
|
safe_cast<RubyPort::SenderState*>(pkt->senderState);
|
|
// @todo This is a dangerous assumption on nothing else
|
|
// modifying the senderState
|
|
RubyTester::SenderState* testerSenderState =
|
|
safe_cast<RubyTester::SenderState*>(reqSenderState->predecessor);
|
|
testerSenderState->subBlock.mergeFrom(data);
|
|
}
|
|
|
|
delete srequest;
|
|
|
|
if (g_system_ptr->m_warmup_enabled) {
|
|
delete pkt;
|
|
g_system_ptr->m_cache_recorder->enqueueNextFetchRequest();
|
|
} else if (g_system_ptr->m_cooldown_enabled) {
|
|
delete pkt;
|
|
g_system_ptr->m_cache_recorder->enqueueNextFlushRequest();
|
|
} else {
|
|
ruby_hit_callback(pkt);
|
|
}
|
|
}
|
|
|
|
bool
|
|
Sequencer::empty() const
|
|
{
|
|
return m_writeRequestTable.empty() && m_readRequestTable.empty();
|
|
}
|
|
|
|
RequestStatus
|
|
Sequencer::makeRequest(PacketPtr pkt)
|
|
{
|
|
if (m_outstanding_count >= m_max_outstanding_requests) {
|
|
return RequestStatus_BufferFull;
|
|
}
|
|
|
|
RubyRequestType primary_type = RubyRequestType_NULL;
|
|
RubyRequestType secondary_type = RubyRequestType_NULL;
|
|
|
|
if (pkt->isLLSC()) {
|
|
//
|
|
// Alpha LL/SC instructions need to be handled carefully by the cache
|
|
// coherence protocol to ensure they follow the proper semantics. In
|
|
// particular, by identifying the operations as atomic, the protocol
|
|
// should understand that migratory sharing optimizations should not
|
|
// be performed (i.e. a load between the LL and SC should not steal
|
|
// away exclusive permission).
|
|
//
|
|
if (pkt->isWrite()) {
|
|
DPRINTF(RubySequencer, "Issuing SC\n");
|
|
primary_type = RubyRequestType_Store_Conditional;
|
|
} else {
|
|
DPRINTF(RubySequencer, "Issuing LL\n");
|
|
assert(pkt->isRead());
|
|
primary_type = RubyRequestType_Load_Linked;
|
|
}
|
|
secondary_type = RubyRequestType_ATOMIC;
|
|
} else if (pkt->req->isLocked()) {
|
|
//
|
|
// x86 locked instructions are translated to store cache coherence
|
|
// requests because these requests should always be treated as read
|
|
// exclusive operations and should leverage any migratory sharing
|
|
// optimization built into the protocol.
|
|
//
|
|
if (pkt->isWrite()) {
|
|
DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
|
|
primary_type = RubyRequestType_Locked_RMW_Write;
|
|
} else {
|
|
DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
|
|
assert(pkt->isRead());
|
|
primary_type = RubyRequestType_Locked_RMW_Read;
|
|
}
|
|
secondary_type = RubyRequestType_ST;
|
|
} else {
|
|
if (pkt->isRead()) {
|
|
if (pkt->req->isInstFetch()) {
|
|
primary_type = secondary_type = RubyRequestType_IFETCH;
|
|
} else {
|
|
#if THE_ISA == X86_ISA
|
|
uint32_t flags = pkt->req->getFlags();
|
|
bool storeCheck = flags &
|
|
(TheISA::StoreCheck << TheISA::FlagShift);
|
|
#else
|
|
bool storeCheck = false;
|
|
#endif // X86_ISA
|
|
if (storeCheck) {
|
|
primary_type = RubyRequestType_RMW_Read;
|
|
secondary_type = RubyRequestType_ST;
|
|
} else {
|
|
primary_type = secondary_type = RubyRequestType_LD;
|
|
}
|
|
}
|
|
} else if (pkt->isWrite()) {
|
|
//
|
|
// Note: M5 packets do not differentiate ST from RMW_Write
|
|
//
|
|
primary_type = secondary_type = RubyRequestType_ST;
|
|
} else if (pkt->isFlush()) {
|
|
primary_type = secondary_type = RubyRequestType_FLUSH;
|
|
} else {
|
|
panic("Unsupported ruby packet type\n");
|
|
}
|
|
}
|
|
|
|
RequestStatus status = insertRequest(pkt, primary_type);
|
|
if (status != RequestStatus_Ready)
|
|
return status;
|
|
|
|
issueRequest(pkt, secondary_type);
|
|
|
|
// TODO: issue hardware prefetches here
|
|
return RequestStatus_Issued;
|
|
}
|
|
|
|
void
|
|
Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
|
|
{
|
|
assert(pkt != NULL);
|
|
int proc_id = -1;
|
|
if (pkt->req->hasContextId()) {
|
|
proc_id = pkt->req->contextId();
|
|
}
|
|
|
|
// If valid, copy the pc to the ruby request
|
|
Addr pc = 0;
|
|
if (pkt->req->hasPC()) {
|
|
pc = pkt->req->getPC();
|
|
}
|
|
|
|
RubyRequest *msg = new RubyRequest(clockEdge(), pkt->getAddr(),
|
|
pkt->getPtr<uint8_t>(true),
|
|
pkt->getSize(), pc, secondary_type,
|
|
RubyAccessMode_Supervisor, pkt,
|
|
PrefetchBit_No, proc_id);
|
|
|
|
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
|
|
curTick(), m_version, "Seq", "Begin", "", "",
|
|
msg->getPhysicalAddress(),
|
|
RubyRequestType_to_string(secondary_type));
|
|
|
|
Cycles latency(0); // initialzed to an null value
|
|
|
|
if (secondary_type == RubyRequestType_IFETCH)
|
|
latency = m_instCache_ptr->getLatency();
|
|
else
|
|
latency = m_dataCache_ptr->getLatency();
|
|
|
|
// Send the message to the cache controller
|
|
assert(latency > 0);
|
|
|
|
assert(m_mandatory_q_ptr != NULL);
|
|
m_mandatory_q_ptr->enqueue(msg, latency);
|
|
}
|
|
|
|
template <class KEY, class VALUE>
|
|
std::ostream &
|
|
operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
|
|
{
|
|
typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
|
|
typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
|
|
|
|
out << "[";
|
|
for (; i != end; ++i)
|
|
out << " " << i->first << "=" << i->second;
|
|
out << " ]";
|
|
|
|
return out;
|
|
}
|
|
|
|
void
|
|
Sequencer::print(ostream& out) const
|
|
{
|
|
out << "[Sequencer: " << m_version
|
|
<< ", outstanding requests: " << m_outstanding_count
|
|
<< ", read request table: " << m_readRequestTable
|
|
<< ", write request table: " << m_writeRequestTable
|
|
<< "]";
|
|
}
|
|
|
|
// this can be called from setState whenever coherence permissions are
|
|
// upgraded when invoked, coherence violations will be checked for the
|
|
// given block
|
|
void
|
|
Sequencer::checkCoherence(const Address& addr)
|
|
{
|
|
#ifdef CHECK_COHERENCE
|
|
g_system_ptr->checkGlobalCoherenceInvariant(addr);
|
|
#endif
|
|
}
|
|
|
|
void
|
|
Sequencer::recordRequestType(SequencerRequestType requestType) {
|
|
DPRINTF(RubyStats, "Recorded statistic: %s\n",
|
|
SequencerRequestType_to_string(requestType));
|
|
}
|
|
|
|
|
|
void
|
|
Sequencer::evictionCallback(const Address& address)
|
|
{
|
|
ruby_eviction_callback(address);
|
|
}
|