507 lines
15 KiB
C++
507 lines
15 KiB
C++
/*
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/arm/isa.hh"
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#include "arch/arm/miscregs.hh"
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#include "base/misc.hh"
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namespace ArmISA
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{
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MiscRegIndex
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decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
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{
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switch(crn) {
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case 0:
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switch (opc2) {
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case 0:
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switch (crm) {
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case 0:
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return MISCREG_DBGDIDR;
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case 1:
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return MISCREG_DBGDSCR_INT;
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default:
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warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
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crn, opc1, crm, opc2);
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return NUM_MISCREGS;
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}
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default:
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warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
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crn, opc1, crm, opc2);
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return NUM_MISCREGS;
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}
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default:
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warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
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crn, opc1, crm, opc2);
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return NUM_MISCREGS;
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}
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}
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MiscRegIndex
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decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
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{
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switch (crn) {
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case 0:
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switch (opc1) {
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case 0:
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switch (crm) {
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case 0:
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switch (opc2) {
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case 1:
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return MISCREG_CTR;
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case 2:
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return MISCREG_TCMTR;
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case 3:
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return MISCREG_TLBTR;
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case 5:
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return MISCREG_MPIDR;
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default:
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return MISCREG_MIDR;
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}
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break;
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case 1:
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switch (opc2) {
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case 0:
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return MISCREG_ID_PFR0;
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case 1:
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return MISCREG_ID_PFR1;
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case 2:
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return MISCREG_ID_DFR0;
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case 3:
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return MISCREG_ID_AFR0;
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case 4:
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return MISCREG_ID_MMFR0;
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case 5:
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return MISCREG_ID_MMFR1;
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case 6:
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return MISCREG_ID_MMFR2;
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case 7:
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return MISCREG_ID_MMFR3;
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}
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break;
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case 2:
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switch (opc2) {
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case 0:
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return MISCREG_ID_ISAR0;
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case 1:
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return MISCREG_ID_ISAR1;
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case 2:
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return MISCREG_ID_ISAR2;
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case 3:
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return MISCREG_ID_ISAR3;
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case 4:
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return MISCREG_ID_ISAR4;
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case 5:
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return MISCREG_ID_ISAR5;
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case 6:
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case 7:
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return MISCREG_RAZ; // read as zero
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}
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break;
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default:
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return MISCREG_RAZ; // read as zero
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}
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break;
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case 1:
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if (crm == 0) {
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switch (opc2) {
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case 0:
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return MISCREG_CCSIDR;
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case 1:
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return MISCREG_CLIDR;
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case 7:
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return MISCREG_AIDR;
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}
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}
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break;
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case 2:
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if (crm == 0 && opc2 == 0) {
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return MISCREG_CSSELR;
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}
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break;
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}
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break;
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case 1:
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if (opc1 == 0) {
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if (crm == 0) {
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switch (opc2) {
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case 0:
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return MISCREG_SCTLR;
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case 1:
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return MISCREG_ACTLR;
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case 0x2:
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return MISCREG_CPACR;
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}
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} else if (crm == 1) {
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switch (opc2) {
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case 0:
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return MISCREG_SCR;
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case 1:
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return MISCREG_SDER;
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case 2:
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return MISCREG_NSACR;
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}
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}
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}
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break;
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case 2:
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if (opc1 == 0 && crm == 0) {
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switch (opc2) {
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case 0:
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return MISCREG_TTBR0;
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case 1:
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return MISCREG_TTBR1;
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case 2:
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return MISCREG_TTBCR;
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}
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}
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break;
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case 3:
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if (opc1 == 0 && crm == 0 && opc2 == 0) {
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return MISCREG_DACR;
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}
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break;
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case 5:
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if (opc1 == 0) {
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if (crm == 0) {
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if (opc2 == 0) {
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return MISCREG_DFSR;
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} else if (opc2 == 1) {
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return MISCREG_IFSR;
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}
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} else if (crm == 1) {
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if (opc2 == 0) {
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return MISCREG_ADFSR;
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} else if (opc2 == 1) {
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return MISCREG_AIFSR;
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}
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}
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}
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break;
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case 6:
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if (opc1 == 0 && crm == 0) {
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switch (opc2) {
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case 0:
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return MISCREG_DFAR;
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case 2:
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return MISCREG_IFAR;
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}
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}
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break;
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case 7:
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if (opc1 == 0) {
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switch (crm) {
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case 0:
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if (opc2 == 4) {
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return MISCREG_NOP;
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}
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break;
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case 1:
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switch (opc2) {
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case 0:
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return MISCREG_ICIALLUIS;
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case 6:
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return MISCREG_BPIALLIS;
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}
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break;
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case 4:
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if (opc2 == 0) {
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return MISCREG_PAR;
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}
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break;
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case 5:
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switch (opc2) {
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case 0:
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return MISCREG_ICIALLU;
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case 1:
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return MISCREG_ICIMVAU;
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case 4:
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return MISCREG_CP15ISB;
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case 6:
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return MISCREG_BPIALL;
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case 7:
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return MISCREG_BPIMVA;
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}
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break;
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case 6:
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if (opc2 == 1) {
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return MISCREG_DCIMVAC;
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} else if (opc2 == 2) {
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return MISCREG_DCISW;
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}
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break;
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case 8:
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switch (opc2) {
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case 0:
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return MISCREG_V2PCWPR;
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case 1:
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return MISCREG_V2PCWPW;
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case 2:
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return MISCREG_V2PCWUR;
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case 3:
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return MISCREG_V2PCWUW;
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case 4:
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return MISCREG_V2POWPR;
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case 5:
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return MISCREG_V2POWPW;
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case 6:
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return MISCREG_V2POWUR;
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case 7:
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return MISCREG_V2POWUW;
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}
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break;
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case 10:
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switch (opc2) {
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case 1:
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return MISCREG_DCCMVAC;
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case 2:
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return MISCREG_MCCSW;
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case 4:
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return MISCREG_CP15DSB;
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case 5:
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return MISCREG_CP15DMB;
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}
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break;
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case 11:
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if (opc2 == 1) {
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return MISCREG_DCCMVAU;
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}
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break;
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case 13:
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if (opc2 == 1) {
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return MISCREG_NOP;
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}
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break;
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case 14:
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if (opc2 == 1) {
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return MISCREG_DCCIMVAC;
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} else if (opc2 == 2) {
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return MISCREG_DCCISW;
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}
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break;
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}
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}
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break;
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case 8:
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if (opc1 == 0) {
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switch (crm) {
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case 3:
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switch (opc2) {
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case 0:
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return MISCREG_TLBIALLIS;
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case 1:
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return MISCREG_TLBIMVAIS;
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case 2:
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return MISCREG_TLBIASIDIS;
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case 3:
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return MISCREG_TLBIMVAAIS;
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}
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break;
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case 5:
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switch (opc2) {
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case 0:
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return MISCREG_ITLBIALL;
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case 1:
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return MISCREG_ITLBIMVA;
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case 2:
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return MISCREG_ITLBIASID;
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}
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break;
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case 6:
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switch (opc2) {
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case 0:
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return MISCREG_DTLBIALL;
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case 1:
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return MISCREG_DTLBIMVA;
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case 2:
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return MISCREG_DTLBIASID;
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}
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break;
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case 7:
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switch (opc2) {
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case 0:
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return MISCREG_TLBIALL;
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case 1:
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return MISCREG_TLBIMVA;
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case 2:
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return MISCREG_TLBIASID;
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case 3:
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return MISCREG_TLBIMVAA;
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}
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break;
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}
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}
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break;
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case 9:
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if (opc1 == 0) {
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switch (crm) {
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case 12:
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switch (opc2) {
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case 0:
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return MISCREG_PMCR;
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case 1:
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return MISCREG_PMCNTENSET;
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case 2:
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return MISCREG_PMCNTENCLR;
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case 3:
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return MISCREG_PMOVSR;
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case 4:
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return MISCREG_PMSWINC;
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case 5:
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return MISCREG_PMSELR;
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case 6:
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return MISCREG_PMCEID0;
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case 7:
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return MISCREG_PMCEID1;
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}
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break;
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case 13:
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switch (opc2) {
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case 0:
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return MISCREG_PMCCNTR;
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case 1:
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return MISCREG_PMC_OTHER;
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case 2:
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return MISCREG_PMXEVCNTR;
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}
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break;
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case 14:
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switch (opc2) {
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case 0:
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return MISCREG_PMUSERENR;
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case 1:
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return MISCREG_PMINTENSET;
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case 2:
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return MISCREG_PMINTENCLR;
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}
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break;
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}
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} else if (opc1 == 1) {
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switch (crm) {
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case 0:
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switch (opc2) {
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case 2: // L2CTLR, L2 Control Register
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return MISCREG_L2CTLR;
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default:
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warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n",
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crn,crm, opc1,opc2);
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break;
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}
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break;
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default:
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return MISCREG_L2LATENCY;
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}
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}
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//Reserved for Branch Predictor, Cache and TCM operations
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break;
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case 10:
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if (opc1 == 0) {
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// crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
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if (crm == 2) { // TEX Remap Registers
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if (opc2 == 0) {
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return MISCREG_PRRR;
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} else if (opc2 == 1) {
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return MISCREG_NMRR;
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}
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}
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}
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break;
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case 11:
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if (opc1 <=7) {
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switch (crm) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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case 8:
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case 15:
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// Reserved for DMA operations for TCM access
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break;
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}
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}
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break;
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case 12:
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if (opc1 == 0) {
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if (crm == 0) {
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if (opc2 == 0) {
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return MISCREG_VBAR;
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} else if (opc2 == 1) {
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return MISCREG_MVBAR;
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}
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} else if (crm == 1) {
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if (opc2 == 0) {
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return MISCREG_ISR;
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}
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}
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}
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break;
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case 13:
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if (opc1 == 0) {
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if (crm == 0) {
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switch (opc2) {
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case 0:
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return MISCREG_FCEIDR;
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case 1:
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return MISCREG_CONTEXTIDR;
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case 2:
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return MISCREG_TPIDRURW;
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case 3:
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return MISCREG_TPIDRURO;
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case 4:
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return MISCREG_TPIDRPRW;
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}
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}
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}
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break;
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case 15:
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// Implementation defined
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return MISCREG_CRN15;
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}
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// Unrecognized register
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return NUM_MISCREGS;
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}
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}
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