101 lines
3.9 KiB
C++
101 lines
3.9 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_LINUX_SYSTEM_HH__
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#define __ARCH_ARM_LINUX_SYSTEM_HH__
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#include <string>
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#include <vector>
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#include "arch/arm/system.hh"
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#include "kern/linux/events.hh"
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#include "params/LinuxArmSystem.hh"
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class LinuxArmSystem : public ArmSystem
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{
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public:
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/** Boilerplate params code */
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typedef LinuxArmSystemParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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LinuxArmSystem(Params *p);
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~LinuxArmSystem();
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void initState();
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bool adderBootUncacheable(Addr a);
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private:
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#ifndef NDEBUG
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/** Event to halt the simulator if the kernel calls panic() */
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BreakPCEvent *kernelPanicEvent;
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#endif
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/**
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* PC based event to skip udelay(<time>) calls and quiesce the
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* processor for the appropriate amount of time. This is not functionally
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* required but does speed up simulation.
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*/
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Linux::UDelayEvent *uDelaySkipEvent;
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/** Another PC based skip event for const_udelay(). Similar to the udelay
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* skip, but this function precomputes the first multiply that is done
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* in the generic case since the parameter is known at compile time.
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* Thus we need to do some division to get back to us.
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*/
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Linux::UDelayEvent *constUDelaySkipEvent;
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/** These variables store addresses of important data structures
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* that are normaly kept coherent at boot with cache mainetence operations.
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* Since these operations aren't supported in gem5, we keep them coherent
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* by making them uncacheable until all processors in the system boot.
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*/
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Addr secDataPtrAddr;
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Addr secDataAddr;
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Addr penReleaseAddr;
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};
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#endif // __ARCH_ARM_LINUX_SYSTEM_HH__
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