04745696b6
SConscript: Added new CPU files to build. arch/alpha/isa_desc: Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed. arch/isa_parser.py: Added new CPU exec method. base/statistics.hh: Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up. base/traceflags.py: Added new CPU trace flags. cpu/static_inst.hh: Changed static inst to use a file that defines the execute functions. --HG-- extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
264 lines
6 KiB
C++
264 lines
6 KiB
C++
#ifndef __ROB_IMPL_HH__
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#define __ROB_IMPL_HH__
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#include "cpu/beta_cpu/rob.hh"
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template<class Impl>
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ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth)
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: numEntries(_numEntries),
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squashWidth(_squashWidth),
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numInstsInROB(0),
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squashedSeqNum(0)
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{
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doneSquashing = true;
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}
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template<class Impl>
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void
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ROB<Impl>::setCPU(FullCPU *cpu_ptr)
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{
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cpu = cpu_ptr;
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tail = cpu->instList.begin();
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squashIt = cpu->instList.end();
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}
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template<class Impl>
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int
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ROB<Impl>::countInsts()
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{
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/*
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int return_val = 0;
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// Iterate through the ROB from the head to the tail, counting the
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// entries.
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for (InstIt i = cpu->instList.begin(); i != tail; i++)
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{
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assert(i != cpu->instList.end());
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return_val++;
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}
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return return_val;
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*/
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// Because the head won't be tracked properly until the ROB gets the
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// first instruction, and any time that the ROB is empty and has not
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// yet gotten the instruction, this function doesn't work.
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return numInstsInROB;
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}
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template<class Impl>
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void
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ROB<Impl>::insertInst(DynInst *inst)
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{
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// Make sure we have the right number of instructions.
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assert(numInstsInROB == countInsts());
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// Make sure the instruction is valid.
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assert(inst);
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DPRINTF(ROB, "ROB: Adding inst PC %#x to the ROB.\n", inst->readPC());
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// If the ROB is full then exit.
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assert(numInstsInROB != numEntries);
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++numInstsInROB;
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// Increment the tail iterator, moving it one instruction back.
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// There is a special case if the ROB was empty prior to this insertion,
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// in which case the tail will be pointing at instList.end(). If that
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// happens, then reset the tail to the beginning of the list.
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if (tail != cpu->instList.end()) {
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tail++;
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} else {
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tail = cpu->instList.begin();
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}
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// Make sure the tail iterator is actually pointing at the instruction
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// added.
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assert((*tail) == inst);
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DPRINTF(ROB, "ROB: Now has %d instructions.\n", numInstsInROB);
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}
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// Whatever calls this function needs to ensure that it properly frees up
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// registers prior to this function.
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template<class Impl>
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void
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ROB<Impl>::retireHead()
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{
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assert(numInstsInROB == countInsts());
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DynInst *head_inst;
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// Get the head ROB instruction.
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head_inst = cpu->instList.front();
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// Make certain this can retire.
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assert(head_inst->readyToCommit());
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DPRINTF(ROB, "ROB: Retiring head instruction of the ROB, "
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"instruction PC %#x, seq num %i\n", head_inst->readPC(),
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head_inst->seqNum);
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// Keep track of how many instructions are in the ROB.
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--numInstsInROB;
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// Tell CPU to remove the instruction from the list of instructions.
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// A special case is needed if the instruction being retired is the
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// only instruction in the ROB; otherwise the tail iterator will become
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// invalidated.
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if (tail == cpu->instList.begin()) {
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cpu->removeFrontInst(head_inst);
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tail = cpu->instList.end();
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} else {
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cpu->removeFrontInst(head_inst);
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}
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}
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template<class Impl>
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bool
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ROB<Impl>::isHeadReady()
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{
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if (numInstsInROB != 0) {
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DynInst *head_inst = cpu->instList.front();
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return head_inst->readyToCommit();
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}
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return false;
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}
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template<class Impl>
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unsigned
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ROB<Impl>::numFreeEntries()
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{
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assert(numInstsInROB == countInsts());
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return numEntries - numInstsInROB;
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}
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template<class Impl>
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void
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ROB<Impl>::doSquash()
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{
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DPRINTF(ROB, "ROB: Squashing instructions.\n");
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assert(squashIt != cpu->instList.end());
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for (int numSquashed = 0;
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numSquashed < squashWidth && (*squashIt)->seqNum != squashedSeqNum;
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++numSquashed)
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{
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// Ensure that the instruction is younger.
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assert((*squashIt)->seqNum > squashedSeqNum);
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DPRINTF(ROB, "ROB: Squashing instruction PC %#x, seq num %i.\n",
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(*squashIt)->readPC(), (*squashIt)->seqNum);
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// Mark the instruction as squashed, and ready to commit so that
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// it can drain out of the pipeline.
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(*squashIt)->setSquashed();
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(*squashIt)->setCanCommit();
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#ifndef FULL_SYSTEM
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if (squashIt == cpu->instList.begin()) {
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DPRINTF(ROB, "ROB: Reached head of instruction list while "
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"squashing.\n");
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squashIt = cpu->instList.end();
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doneSquashing = true;
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return;
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}
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#endif
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// Move the tail iterator to the next instruction.
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squashIt--;
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}
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// Check if ROB is done squashing.
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if ((*squashIt)->seqNum == squashedSeqNum) {
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DPRINTF(ROB, "ROB: Done squashing instructions.\n");
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squashIt = cpu->instList.end();
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doneSquashing = true;
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}
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}
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template<class Impl>
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void
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ROB<Impl>::squash(InstSeqNum squash_num)
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{
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DPRINTF(ROB, "ROB: Starting to squash within the ROB.\n");
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doneSquashing = false;
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squashedSeqNum = squash_num;
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assert(tail != cpu->instList.end());
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squashIt = tail;
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doSquash();
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}
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template<class Impl>
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uint64_t
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ROB<Impl>::readHeadPC()
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{
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assert(numInstsInROB == countInsts());
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DynInst *head_inst = cpu->instList.front();
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return head_inst->readPC();
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}
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template<class Impl>
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uint64_t
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ROB<Impl>::readHeadNextPC()
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{
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assert(numInstsInROB == countInsts());
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DynInst *head_inst = cpu->instList.front();
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return head_inst->readNextPC();
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}
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template<class Impl>
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InstSeqNum
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ROB<Impl>::readHeadSeqNum()
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{
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// Return the last sequence number that has not been squashed. Other
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// stages can use it to squash any instructions younger than the current
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// tail.
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DynInst *head_inst = cpu->instList.front();
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return head_inst->seqNum;
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}
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template<class Impl>
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uint64_t
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ROB<Impl>::readTailPC()
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{
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assert(numInstsInROB == countInsts());
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assert(tail != cpu->instList.end());
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return (*tail)->readPC();
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}
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template<class Impl>
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InstSeqNum
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ROB<Impl>::readTailSeqNum()
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{
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// Return the last sequence number that has not been squashed. Other
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// stages can use it to squash any instructions younger than the current
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// tail.
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return (*tail)->seqNum;
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}
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#endif // __ROB_IMPL_HH__
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