04745696b6
SConscript: Added new CPU files to build. arch/alpha/isa_desc: Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed. arch/isa_parser.py: Added new CPU exec method. base/statistics.hh: Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up. base/traceflags.py: Added new CPU trace flags. cpu/static_inst.hh: Changed static inst to use a file that defines the execute functions. --HG-- extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
244 lines
7.3 KiB
C++
244 lines
7.3 KiB
C++
#ifndef __INST_QUEUE_HH__
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#define __INST_QUEUE_HH__
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#include <list>
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#include <queue>
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#include <stdint.h>
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#include "base/timebuf.hh"
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using namespace std;
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//Perhaps have a better separation between the data structure underlying
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//and the actual algorithm.
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//somewhat nasty to try to have a nice ordering.
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// Consider moving to STL list or slist for the LL stuff.
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/**
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* A standard instruction queue class. It holds instructions in an
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* array, holds the ordering of the instructions within a linked list,
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* and tracks producer/consumer dependencies within a separate linked
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* list. Similar to the rename map and the free list, it expects that
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* floating point registers have their indices start after the integer
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* registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
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* and 96-191 are fp). This remains true even for both logical and
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* physical register indices.
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*/
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template<class Impl>
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class InstructionQueue
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{
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public:
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//Typedefs from the Impl.
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::Params Params;
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typedef typename Impl::IssueStruct IssueStruct;
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typedef typename Impl::TimeStruct TimeStruct;
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// Typedef of iterator through the list of instructions. Might be
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// better to untie this from the FullCPU or pass its information to
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// the stages.
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typedef typename list<DynInst *>::iterator ListIt;
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/**
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* Class for priority queue entries. Mainly made so that the < operator
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* is defined.
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*/
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struct ReadyEntry {
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DynInst *inst;
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ReadyEntry(DynInst *_inst)
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: inst(_inst)
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{ }
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/** Compare(lhs,rhs) checks if rhs is "bigger" than lhs. If so, rhs
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* goes higher on the priority queue. The oldest instruction should
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* be on the top of the instruction queue, so in this case "bigger"
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* has the reverse meaning; the instruction with the lowest
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* sequence number is on the top.
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*/
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bool operator <(const ReadyEntry &rhs) const
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{
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if (this->inst->seqNum > rhs.inst->seqNum)
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return true;
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return false;
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}
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};
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InstructionQueue(Params ¶ms);
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void setCPU(FullCPU *cpu);
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void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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unsigned numFreeEntries();
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bool isFull();
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void insert(DynInst *new_inst);
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void advanceTail(DynInst *inst);
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void scheduleReadyInsts();
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void wakeDependents(DynInst *completed_inst);
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void doSquash();
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void squash();
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void stopSquash();
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private:
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/** Debugging function to count how many entries are in the IQ. It does
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* a linear walk through the instructions, so do not call this function
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* during normal execution.
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*/
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int countInsts();
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private:
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/** Pointer to the CPU. */
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FullCPU *cpu;
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/** The queue to the execute stage. Issued instructions will be written
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* into it.
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*/
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TimeBuffer<IssueStruct> *issueToExecuteQueue;
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/** The backwards time buffer. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to read information from timebuffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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enum InstList {
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Int,
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Float,
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Branch,
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Squashed,
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None
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};
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/** List of ready int instructions. Used to keep track of the order in
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* which */
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priority_queue<ReadyEntry> readyIntInsts;
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/** List of ready floating point instructions. */
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priority_queue<ReadyEntry> readyFloatInsts;
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/** List of ready branch instructions. */
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priority_queue<ReadyEntry> readyBranchInsts;
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/** List of squashed instructions (which are still valid and in IQ).
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* Implemented using a priority queue; the entries must contain both
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* the IQ index and sequence number of each instruction so that
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* ordering based on sequence numbers can be used.
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*/
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priority_queue<ReadyEntry> squashedInsts;
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/** Number of free IQ entries left. */
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unsigned freeEntries;
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/** The number of entries in the instruction queue. */
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unsigned numEntries;
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/** The number of integer instructions that can be issued in one
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* cycle.
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*/
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unsigned intWidth;
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/** The number of floating point instructions that can be issued
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* in one cycle.
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*/
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unsigned floatWidth;
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/** The number of branches that can be issued in one cycle. */
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unsigned branchWidth;
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/** The total number of instructions that can be issued in one cycle. */
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unsigned totalWidth;
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//The number of physical registers in the CPU.
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unsigned numPhysRegs;
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/** The number of physical integer registers in the CPU. */
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unsigned numPhysIntRegs;
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/** The number of floating point registers in the CPU. */
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unsigned numPhysFloatRegs;
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/** Delay between commit stage and the IQ.
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* @todo: Make there be a distinction between the delays within IEW.
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*/
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unsigned commitToIEWDelay;
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//////////////////////////////////
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// Variables needed for squashing
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//////////////////////////////////
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/** The sequence number of the squashed instruction. */
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InstSeqNum squashedSeqNum;
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/** Iterator that points to the oldest instruction in the IQ. */
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ListIt head;
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/** Iterator that points to the youngest instruction in the IQ. */
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ListIt tail;
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/** Iterator that points to the last instruction that has been squashed.
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* This will not be valid unless the IQ is in the process of squashing.
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*/
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ListIt squashIt;
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///////////////////////////////////
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// Dependency graph stuff
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///////////////////////////////////
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class DependencyEntry
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{
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public:
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DynInst *inst;
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//Might want to include data about what arch. register the
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//dependence is waiting on.
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DependencyEntry *next;
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//This function, and perhaps this whole class, stand out a little
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//bit as they don't fit a classification well. I want access
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//to the underlying structure of the linked list, yet at
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//the same time it feels like this should be something abstracted
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//away. So for now it will sit here, within the IQ, until
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//a better implementation is decided upon.
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// This function probably shouldn't be within the entry...
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void insert(DynInst *new_inst);
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void remove(DynInst *inst_to_remove);
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};
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/** Array of linked lists. Each linked list is a list of all the
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* instructions that depend upon a given register. The actual
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* register's index is used to index into the graph; ie all
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* instructions in flight that are dependent upon r34 will be
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* in the linked list of dependGraph[34].
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*/
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DependencyEntry *dependGraph;
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/** A cache of the recently woken registers. It is 1 if the register
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* has been woken up recently, and 0 if the register has been added
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* to the dependency graph and has not yet received its value. It
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* is basically a secondary scoreboard, and should pretty much mirror
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* the scoreboard that exists in the rename map.
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*/
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vector<bool> regScoreboard;
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bool addToDependents(DynInst *new_inst);
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void insertDependency(DynInst *new_inst);
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void createDependency(DynInst *new_inst);
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void addIfReady(DynInst *inst);
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};
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#endif //__INST_QUEUE_HH__
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