SConscript: Added new CPU files to build. arch/alpha/isa_desc: Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed. arch/isa_parser.py: Added new CPU exec method. base/statistics.hh: Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up. base/traceflags.py: Added new CPU trace flags. cpu/static_inst.hh: Changed static inst to use a file that defines the execute functions. --HG-- extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
111 lines
2.8 KiB
C++
111 lines
2.8 KiB
C++
#ifndef __COMM_HH__
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#define __COMM_HH__
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#include <stdint.h>
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#include "arch/alpha/isa_traits.hh"
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#include "cpu/inst_seq.hh"
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using namespace std;
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// Find better place to put this typedef.
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typedef short int PhysRegIndex;
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// Might want to put constructors/destructors here.
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template<class Impl>
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struct SimpleFetchSimpleDecode {
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// Consider having a field of how many ready instructions.
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typename Impl::DynInst *insts[1];
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};
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template<class Impl>
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struct SimpleDecodeSimpleRename {
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// Consider having a field of how many ready instructions.
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typename Impl::DynInst *insts[1];
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};
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template<class Impl>
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struct SimpleRenameSimpleIEW {
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// Consider having a field of how many ready instructions.
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typename Impl::DynInst *insts[1];
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};
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template<class Impl>
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struct SimpleIEWSimpleCommit {
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// Consider having a field of how many ready instructions.
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typename Impl::DynInst *insts[1];
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};
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template<class Impl>
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struct IssueStruct {
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typename Impl::DynInst *insts[1];
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};
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struct TimeBufStruct {
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struct decodeComm {
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bool squash;
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bool stall;
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bool predIncorrect;
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uint64_t branchAddr;
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//Question, is it worthwhile to have this Addr passed along
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//by each stage, or just have Fetch look it up in the proper
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//amount of cycles in the time buffer?
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//Both might actually be needed because decode can send a different
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//nextPC if the bpred was wrong.
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uint64_t nextPC;
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};
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decodeComm decodeInfo;
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// Rename can't actually tell anything to squash or send a new PC back
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// because it doesn't do anything along those lines. But maybe leave
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// these fields in here to keep the stages mostly orthagonal.
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struct renameComm {
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bool squash;
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bool stall;
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uint64_t nextPC;
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};
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renameComm renameInfo;
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struct iewComm {
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bool squash;
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bool stall;
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bool predIncorrect;
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// Also eventually include skid buffer space.
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unsigned freeIQEntries;
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uint64_t nextPC;
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// For now hardcode the type.
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// Change this to sequence number eventually.
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InstSeqNum squashedSeqNum;
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};
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iewComm iewInfo;
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struct commitComm {
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bool squash;
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bool stall;
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unsigned freeROBEntries;
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uint64_t nextPC;
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// Think of better names here.
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// Will need to be a variety of sizes...
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// Maybe make it a vector, that way only need one object.
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vector<PhysRegIndex> freeRegs;
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bool robSquashing;
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// Represents the instruction that has either been retired or
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// squashed. Similar to having a single bus that broadcasts the
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// retired or squashed sequence number.
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InstSeqNum doneSeqNum;
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};
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commitComm commitInfo;
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};
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#endif //__COMM_HH__
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