03f740664b
Changeset 11798:3a490c57058d --------------------------- misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10] The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Introduce transactor modules that represent the gem5 ports in the * SystemC world. * Update the SimControl module and let it keep track of the gem5 ports. Reviewed at http://reviews.gem5.org/r/3775/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
139 lines
4.7 KiB
C++
139 lines
4.7 KiB
C++
/*
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* Copyright (c) 2015, University of Kaiserslautern
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Matthias Jung
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* Christian Menard
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*/
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#ifndef __SC_SLAVE_PORT_HH__
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#define __SC_SLAVE_PORT_HH__
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#include <systemc>
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#include <tlm>
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#include "mem/external_slave.hh"
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#include "sc_mm.hh"
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#include "sc_peq.hh"
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#include "sim_control.hh"
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namespace Gem5SystemC
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{
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// forward declaration
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class Gem5SlaveTransactor;
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/**
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* Test that gem5 is at the same time as SystemC
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*/
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#define CAUGHT_UP do { \
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assert(curTick() == sc_core::sc_time_stamp().value()); \
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} while (0)
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/**
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* This is a gem5 slave port that translates gem5 packets to TLM transactions.
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*
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* Upon receiving a packet (recvAtomic, recvTiningReq, recvFunctional) the port
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* creates a new TLM payload and initializes it with information from the gem5
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* packet. The original packet is added as an extension to the TLM payload.
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* Then the port issues a TLM transaction in the SystemC world. By storing the
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* original packet as a payload extension, the packet can be restored and send
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* back to the gem5 world upon receiving a response from the SystemC world.
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*/
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class SCSlavePort : public ExternalSlave::Port
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{
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public:
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/** One instance of pe and the related callback needed */
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//payloadEvent<SCSlavePort> pe;
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void pec(PayloadEvent<SCSlavePort> * pe,
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tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
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/**
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* A transaction after BEGIN_REQ has been sent but before END_REQ, which
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* is blocking the request channel (Exlusion Rule, see IEEE1666)
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*/
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tlm::tlm_generic_payload *blockingRequest;
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/**
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* Did another gem5 request arrive while currently blocked?
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* This variable is needed when a retry should happen
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*/
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bool needToSendRequestRetry;
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/**
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* A response which has been asked to retry by gem5 and so is blocking
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* the response channel
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*/
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tlm::tlm_generic_payload *blockingResponse;
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protected:
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/** The gem5 Port slave interface */
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Tick recvAtomic(PacketPtr packet);
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void recvFunctional(PacketPtr packet);
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bool recvTimingReq(PacketPtr packet);
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bool recvTimingSnoopResp(PacketPtr packet);
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void recvRespRetry();
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void recvFunctionalSnoop(PacketPtr packet);
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Gem5SlaveTransactor* transactor;
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public:
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/** The TLM initiator interface */
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tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
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tlm::tlm_phase& phase,
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sc_core::sc_time& t);
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SCSlavePort(const std::string &name_,
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const std::string &systemc_name,
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ExternalSlave &owner_);
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void bindToTransactor(Gem5SlaveTransactor* transactor);
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friend PayloadEvent<SCSlavePort>;
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};
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class SCSlavePortHandler : public ExternalSlave::Handler
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{
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private:
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Gem5SimControl& control;
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public:
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SCSlavePortHandler(Gem5SimControl& control) : control(control) {}
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ExternalSlave::Port *getExternalPort(const std::string &name,
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ExternalSlave &owner,
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const std::string &port_data);
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};
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}
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#endif // __SC_SLAVE_PORT_H__
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