1223 lines
141 KiB
Text
1223 lines
141 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.233332 # Number of seconds simulated
|
|
sim_ticks 233331881000 # Number of ticks simulated
|
|
final_tick 233331881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 137799 # Simulator instruction rate (inst/s)
|
|
host_op_rate 149285 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 63638999 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 320760 # Number of bytes of host memory used
|
|
host_seconds 3666.49 # Real time elapsed on the host
|
|
sim_insts 505237724 # Number of instructions simulated
|
|
sim_ops 547350945 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu.inst 689792 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 9194752 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.l2cache.prefetcher 16497856 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 26382400 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 689792 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 689792 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 18714240 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 18714240 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.inst 10778 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 143668 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.l2cache.prefetcher 257779 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 412225 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 292410 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 292410 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 2956270 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 39406325 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.l2cache.prefetcher 70705537 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 113068132 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 2956270 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 2956270 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 80204385 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 80204385 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 80204385 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 2956270 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 39406325 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.l2cache.prefetcher 70705537 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 193272517 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 412225 # Number of read requests accepted
|
|
system.physmem.writeReqs 292410 # Number of write requests accepted
|
|
system.physmem.readBursts 412225 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 292410 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 26244608 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 137792 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 18711808 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 26382400 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 18714240 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 2153 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 7 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 26528 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 25303 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 24713 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 27194 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 26607 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 24941 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 24442 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 25767 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 24723 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 25091 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 26187 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 26462 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 26013 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 25052 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 25510 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 18779 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 18326 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 18027 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 17939 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 18703 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 18353 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 17755 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 17808 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 18074 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 17824 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 18093 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 18724 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 18814 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 18339 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 18411 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 18403 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 233331863000 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 412225 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 292410 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 311682 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 49314 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 13194 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 9237 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 7343 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 6192 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 5234 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 4415 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 3338 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 6393 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 6662 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 15393 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 16401 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 16959 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 17206 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 17395 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 17650 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 17892 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 18388 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 18586 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 18721 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 19985 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 18227 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 17652 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 17464 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 29 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 307255 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 146.312346 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 102.902161 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 182.114345 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 184693 60.11% 60.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 81851 26.64% 86.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 16642 5.42% 92.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 7320 2.38% 94.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 4729 1.54% 96.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 2259 0.74% 96.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1737 0.57% 97.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1607 0.52% 97.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 307255 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 23.664070 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 116.589701 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-511 17327 99.99% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 16.872807 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 16.831610 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 1.219578 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16 10506 60.63% 60.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 279 1.61% 62.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 5596 32.29% 94.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 616 3.55% 98.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 141 0.81% 98.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 60 0.35% 99.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::22 44 0.25% 99.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::23 41 0.24% 99.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 25 0.14% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 12 0.07% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 7 0.04% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 9022211140 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 16711061140 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2050360000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 22001.53 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 40751.53 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 112.48 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 80.19 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 113.07 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 80.20 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 1.51 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 21.59 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 299444 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 95740 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 32.74 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 331138.62 # Average gap between requests
|
|
system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 1156823640 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 631203375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1601035800 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 944071200 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 75187551735 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 74044498500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 168805201770 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 723.458661 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 122654182736 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 7791420000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 102885452264 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 1166024160 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 636223500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1597377600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 950499360 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 74554879950 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 74599507500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 168744529590 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 723.198461 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 123580654566 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 7791420000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 101958813184 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 175090137 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 131338905 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 7443529 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 90540858 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 83879425 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 92.642622 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 12110692 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 466663763 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 7839248 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 731808788 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 175090137 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 95990117 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 450472274 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 14939659 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 5656 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 14269 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 236720425 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 34587 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 465801433 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.701462 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.179511 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 93869731 20.15% 20.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 132699774 28.49% 48.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 57852108 12.42% 61.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 181379820 38.94% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 465801433 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.375195 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.568171 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32373679 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 117343382 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 287062106 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 22041011 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 6981255 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 24049971 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 496386 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 715809364 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 30003912 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 6981255 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 63434666 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 54211510 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 40338612 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 276664591 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 24170799 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 686600417 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 13340367 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 9416739 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2386420 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1670076 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 1927738 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 831025477 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3019202538 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 723925996 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 176901726 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1544701 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 1534906 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 42308307 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 143530339 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 67981565 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 12860716 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 11266999 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 668170903 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2978331 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 610248763 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 5854866 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 123798289 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 319264737 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 699 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 465801433 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.310105 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.101429 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 148653685 31.91% 31.91% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 101184506 21.72% 53.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 145749505 31.29% 84.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 63290175 13.59% 98.51% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 6923088 1.49% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 474 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 465801433 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 71924616 52.97% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 44553347 32.81% 85.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 19296722 14.21% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 413148587 67.70% 67.70% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 351752 0.06% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 134215566 21.99% 89.75% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 62532855 10.25% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 610248763 # Type of FU issued
|
|
system.cpu.iq.rate 1.307684 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 135774715 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.222491 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1827928247 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 794975703 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 594980555 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 746023301 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 7276983 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 27645583 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 25497 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 28922 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 11121088 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 225125 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 22421 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 6981255 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 22978687 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 924846 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 672636723 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 143530339 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 67981565 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1489789 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 258799 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 529739 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 28922 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3821583 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3731049 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 7552632 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 599397786 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 129576337 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 10850977 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1487489 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 190533026 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 131372234 # Number of branches executed
|
|
system.cpu.iew.exec_stores 60956689 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.284432 # Inst execution rate
|
|
system.cpu.iew.wb_sent 596275489 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 594980571 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 349907425 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 570632122 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.274966 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.613193 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 110027797 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 6954955 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 448686365 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.222892 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.888131 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 219669318 48.96% 48.96% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 116312485 25.92% 74.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 43742979 9.75% 84.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 23278779 5.19% 89.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 11577691 2.58% 92.40% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 7777719 1.73% 94.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 8261206 1.84% 95.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 4236050 0.94% 96.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 13830138 3.08% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 448686365 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 506581608 # Number of instructions committed
|
|
system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 172745233 # Number of memory references committed
|
|
system.cpu.commit.loads 115884756 # Number of loads committed
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
system.cpu.commit.branches 121548302 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 13830138 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 1093571715 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1334590067 # The number of ROB writes
|
|
system.cpu.timesIdled 13966 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 862330 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 505237724 # Number of Instructions Simulated
|
|
system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.923652 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.923652 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.082659 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.082659 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 611088796 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 328119086 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 2170176811 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 376539852 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 217970841 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 2820945 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.631358 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 169354520 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2821457 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 60.023782 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 498530000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.631358 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999280 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999280 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 356242117 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 356242117 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114648793 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114648793 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 51725790 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 51725790 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 166374583 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 166374583 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 166377369 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 166377369 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4842267 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 4842267 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2513516 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2513516 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 7355783 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 7355783 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 7355794 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 7355794 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 56187510500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 56187510500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19050466441 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 19050466441 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1271500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 1271500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 75237976941 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 75237976941 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 75237976941 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 75237976941 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 119491060 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 119491060 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 173730366 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 173730366 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 173733163 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 173733163 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040524 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040524 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046341 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.046341 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.042340 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.042340 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.042340 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.042340 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11603.554802 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11603.554802 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7579.210334 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 7579.210334 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19265.151515 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19265.151515 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10228.411706 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 10228.411706 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10228.396410 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 10228.396410 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 931670 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 221105 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 4.213699 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2357131 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2357131 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540406 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2540406 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1993903 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1993903 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4534309 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4534309 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4534309 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4534309 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301861 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 2301861 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519613 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 519613 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2821474 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2821474 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2821484 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2821484 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28687651000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 28687651000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4620185994 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4620185994 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 674500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 674500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307836994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 33307836994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33308511494 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 33308511494 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019264 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019264 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016241 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016241 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.807702 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.807702 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8891.590461 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8891.590461 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67450 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67450 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11805.119237 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11805.119237 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11805.316455 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11805.316455 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 73454 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 466.198570 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 236637753 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3199.277411 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 114991601500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 466.198570 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.910544 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.910544 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 473514607 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 473514607 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 236637753 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 236637753 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 236637753 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 236637753 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 236637753 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 236637753 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 82554 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 82554 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 82554 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 82554 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 82554 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 82554 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1566745159 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1566745159 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1566745159 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1566745159 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1566745159 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1566745159 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 236720307 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 236720307 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 236720307 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 236720307 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 236720307 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 236720307 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18978.428168 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 18978.428168 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 18978.428168 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 18978.428168 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 198034 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 7006 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 28.266343 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8560 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 8560 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 8560 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 8560 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 8560 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 8560 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73994 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 73994 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 73994 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 73994 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 73994 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 73994 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1278636265 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1278636265 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1278636265 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1278636265 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1278636265 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1278636265 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17280.269549 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17280.269549 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 8511909 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 8513040 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 167 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 743544 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 401080 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 15418.085448 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 5068240 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 417417 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 12.141911 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 34601120500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 8466.854939 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 473.689855 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 4911.860449 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1565.680205 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.516776 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028912 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.299796 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095562 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.941045 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 1090 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15247 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 243 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 815 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1541 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10024 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3332 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066528 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930603 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 93191002 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 93191002 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2357131 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 2357131 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 25 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 516789 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 516789 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63176 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 63176 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2155511 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 2155511 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 63176 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2672300 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2735476 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 63176 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2672300 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2735476 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 5171 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 5171 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10785 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 10785 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 143986 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 143986 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 10785 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 149157 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 159942 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 10785 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 149157 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 159942 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 505481000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 505481000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 792508500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 792508500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11120056000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 11120056000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 792508500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11625537000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 12418045500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 792508500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11625537000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 12418045500 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2357131 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 2357131 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 27 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 521960 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 521960 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73961 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 73961 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299497 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 2299497 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 73961 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2821457 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2895418 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 73961 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2821457 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2895418 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.074074 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.074074 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009907 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.009907 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.145820 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.145820 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.062616 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.062616 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.145820 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.052865 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.055240 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.145820 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.052865 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.055240 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97753.045833 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97753.045833 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73482.475661 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73482.475661 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77230.119595 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77230.119595 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73482.475661 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77941.611859 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 77640.929212 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73482.475661 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77941.611859 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 77640.929212 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 292410 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 292410 # number of writebacks
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1449 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 1449 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 6 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4039 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4039 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 5488 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 5494 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 5488 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 5494 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6957 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 6957 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275571 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 275571 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10779 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10779 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 139947 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 139947 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10779 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143669 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 154448 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10779 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143669 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275571 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 430019 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19018555494 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19018555494 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 33500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 33500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 344223500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 344223500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 727200000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 727200000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9979336000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9979336000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 727200000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10323559500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11050759500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 727200000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10323559500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19018555494 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 30069314994 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007131 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007131 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.145739 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060860 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060860 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.053342 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.148517 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69015.083205 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92483.476625 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92483.476625 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67464.514333 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67464.514333 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71307.966587 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71307.966587 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71550.033021 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69925.549787 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2373490 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 2649541 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 621819 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 317371 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 521960 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 521960 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 73994 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299497 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220555 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440647 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 8661202 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331429632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 336163072 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 718484 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 6508328 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.110389 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 5789877 88.96% 88.96% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 718451 11.04% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 6508328 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5252069500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 111018442 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 4232215467 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 408504 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 292410 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 103085 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 3721 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 3721 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 408504 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219951 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1219951 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45096640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 45096640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 807723 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 807723 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 807723 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 2173813941 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2179181168 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|