03e256b0f0
README:
Clarify cygwin EIO error explanation.
build/SConstruct:
Cygwin header files cause uninitialized var warnings.
dev/ide_ctrl.cc:
Get rid of unnecessary byte-swap calls, some of which were
too ambiguous for cygwin (or gcc 3.4.4).
dev/pcidev.cc:
Disambiguate arg for overloaded byte swap operation
(and fix it to be the correct one).
--HG--
extra : convert_revision : be37c6315aacbec6332b1d09e726b39b4aa18dce
86 lines
3.1 KiB
C++
86 lines
3.1 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Declaration of a fake device.
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*/
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#ifndef __ISA_FAKE_HH__
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#define __ISA_FAKE_HH__
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#include "dev/tsunami.hh"
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#include "base/range.hh"
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#include "dev/io_device.hh"
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/**
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* IsaFake is a device that returns -1 on all reads and
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* accepts all writes. It is meant to be placed at an address range
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* so that an mcheck doesn't occur when an os probes a piece of hw
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* that doesn't exist (e.g. UARTs1-3).
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*/
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class IsaFake : public PioDevice
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{
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private:
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/** The address in memory that we respond to */
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Addr addr;
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public:
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/**
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* The constructor for Tsunmami Fake just registers itself with the MMU.
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* @param name name of this device.
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* @param a address to respond to.
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* @param mmu the mmu we register with.
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* @param size number of addresses to respond to
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*/
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IsaFake(const std::string &name, Addr a, MemoryController *mmu,
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HierParams *hier, Bus *bus, Addr size = 0x8);
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/**
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* This read always returns -1.
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* @param req The memory request.
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* @param data Where to put the data.
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*/
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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/**
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* All writes are simply ignored.
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* @param req The memory request.
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* @param data the data to not write.
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Return how long this access will take.
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* @param req the memory request to calcuate
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* @return Tick when the request is done
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*/
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Tick cacheAccess(MemReqPtr &req);
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};
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#endif // __ISA_FAKE_HH__
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