036a8ceb8d
code into a function that can be called by the AlphaConsole class.
AlphaConsole will pass in its address.
arch/alpha/ev5.hh:
Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable
bits so that they will be converted correctly.
dev/alpha_access.h:
Do not hard code the location of the AlphaConsole
dev/alpha_console.cc:
fixup #includes
tell the system where the alpha console is
sim/system.hh:
Provide a function that will tell the system where the AlphaAccess
structure (device) lives
--HG--
extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
115 lines
4.9 KiB
C++
115 lines
4.9 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ALPHA_EV5_HH__
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#define __ARCH_ALPHA_EV5_HH__
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namespace EV5 {
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#ifdef ALPHA_TLASER
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const uint64_t AsnMask = ULL(0x7f);
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#else
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const uint64_t AsnMask = ULL(0xff);
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#endif
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const int VAddrImplBits = 43;
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const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
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const Addr VAddrUnImplMask = ~VAddrImplMask;
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inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
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inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
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inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
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inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
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inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
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#ifdef ALPHA_TLASER
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inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
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const int PAddrImplBits = 40;
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#else
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inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
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const int PAddrImplBits = 44; // for Tsunami
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#endif
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const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
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const Addr PAddrUncachedBit39 = ULL(0x8000000000);
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const Addr PAddrUncachedBit40 = ULL(0x10000000000);
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const Addr PAddrUncachedBit43 = ULL(0x80000000000);
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const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
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inline Addr Phys2K0Seg(Addr addr)
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{
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#ifndef ALPHA_TLASER
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if (addr & PAddrUncachedBit43) {
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addr &= PAddrUncachedMask;
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addr |= PAddrUncachedBit40;
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}
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#endif
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return addr | AlphaISA::K0SegBase;
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}
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inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
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inline Addr DTB_PTE_PPN(uint64_t reg)
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{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
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inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
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inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
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inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
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inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
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inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
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inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
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inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
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inline Addr ITB_PTE_PPN(uint64_t reg)
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{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
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inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
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inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
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inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
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inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
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inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
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inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
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inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
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inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
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inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
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inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
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inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
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inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
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const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
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const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
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const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
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const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
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const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
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const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
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inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
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inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
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const Addr PalBase = 0x4000;
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const Addr PalMax = 0x10000;
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/* namespace EV5 */ }
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#endif // __ARCH_ALPHA_EV5_HH__
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