2f316082e4
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/full_cpu/op_class.hh: cpu/full_cpu/smt.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/platform.cc: dev/platform.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.hh: dev/tsunamireg.h: docs/stl.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: sim/universe.cc: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/m5/m5.c: util/m5/m5op.h: util/tap/tap.cc: Updated Copyright dev/console.cc: dev/console.hh: This code isn't ours, and shouldn't have our copyright --HG-- extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
627 lines
16 KiB
C++
627 lines
16 KiB
C++
/*
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* Copyright (c) 2001-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sstream>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "sim/builder.hh"
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#include "targetarch/alpha_memory.hh"
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#include "targetarch/ev5.hh"
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using namespace std;
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha TLB
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//
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#ifdef DEBUG
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bool uncacheBit39 = false;
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bool uncacheBit40 = false;
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#endif
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AlphaTLB::AlphaTLB(const string &name, int s)
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: SimObject(name), size(s), nlu(0)
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{
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table = new AlphaISA::PTE[size];
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memset(table, 0, sizeof(AlphaISA::PTE[size]));
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}
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AlphaTLB::~AlphaTLB()
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{
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if (table)
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delete [] table;
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}
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// look up an entry in the TLB
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AlphaISA::PTE *
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AlphaTLB::lookup(Addr vpn, uint8_t asn) const
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{
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DPRINTF(TLB, "lookup %#x\n", vpn);
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i == lookupTable.end())
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return NULL;
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while (i->first == vpn) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (vpn == pte->tag && (pte->asma || pte->asn == asn))
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return pte;
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++i;
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}
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// not found...
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return NULL;
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}
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void
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AlphaTLB::checkCacheability(MemReqPtr &req)
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{
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// in Alpha, cacheability is controlled by upper-level bits of the
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// physical address
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/*
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* We support having the uncacheable bit in either bit 39 or bit 40.
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* The Turbolaser platform (and EV5) support having the bit in 39, but
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* Tsunami (which Linux assumes uses an EV6) generates accesses with
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* the bit in 40. So we must check for both, but we have debug flags
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* to catch a weird case where both are used, which shouldn't happen.
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*/
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if (req->paddr & PA_UNCACHED_BIT_43) {
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// IPR memory space not implemented
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if (PA_IPR_SPACE(req->paddr))
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if (!req->xc->misspeculating())
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panic("IPR memory space not implemented! PA=%x\n",
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req->paddr);
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// mark request as uncacheable
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req->flags |= UNCACHEABLE;
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// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
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req->paddr &= PA_UNCACHED_MASK;
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}
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}
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// insert a new TLB entry
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void
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AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte)
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{
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if (table[nlu].valid) {
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Addr oldvpn = table[nlu].tag;
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PageTable::iterator i = lookupTable.find(oldvpn);
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if (i == lookupTable.end())
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panic("TLB entry not found in lookupTable");
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int index;
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while ((index = i->second) != nlu) {
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if (table[index].tag != oldvpn)
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panic("TLB entry not found in lookupTable");
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++i;
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}
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DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
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lookupTable.erase(i);
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}
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Addr vpn = VA_VPN(vaddr);
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DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vpn, pte.ppn);
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table[nlu] = pte;
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table[nlu].tag = vpn;
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table[nlu].valid = true;
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lookupTable.insert(make_pair(vpn, nlu));
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nextnlu();
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}
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void
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AlphaTLB::flushAll()
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{
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memset(table, 0, sizeof(AlphaISA::PTE[size]));
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lookupTable.clear();
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nlu = 0;
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}
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void
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AlphaTLB::flushProcesses()
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{
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PageTable::iterator i = lookupTable.begin();
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PageTable::iterator end = lookupTable.end();
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while (i != end) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (!pte->asma) {
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DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
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pte->valid = false;
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lookupTable.erase(i);
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}
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++i;
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}
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}
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void
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AlphaTLB::flushAddr(Addr vaddr, uint8_t asn)
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{
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Addr vpn = VA_VPN(vaddr);
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PageTable::iterator i = lookupTable.find(vpn);
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if (i == lookupTable.end())
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return;
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while (i->first == vpn) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
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DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vpn, pte->ppn);
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// invalidate this entry
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pte->valid = false;
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lookupTable.erase(i);
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}
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++i;
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}
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}
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void
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AlphaTLB::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(size);
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SERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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nameOut(os, csprintf("%s.PTE%d", name(), i));
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table[i].serialize(os);
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}
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}
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void
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AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_SCALAR(size);
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UNSERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
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if (table[i].valid) {
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lookupTable.insert(make_pair(table[i].tag, i));
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}
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}
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha ITB
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//
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AlphaITB::AlphaITB(const std::string &name, int size)
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: AlphaTLB(name, size)
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{}
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void
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AlphaITB::regStats()
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{
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hits
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.name(name() + ".hits")
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.desc("ITB hits");
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misses
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.name(name() + ".misses")
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.desc("ITB misses");
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acv
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.name(name() + ".acv")
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.desc("ITB acv");
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accesses
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.name(name() + ".accesses")
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.desc("ITB accesses");
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accesses = hits + misses;
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}
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void
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AlphaITB::fault(Addr pc, ExecContext *xc) const
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{
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uint64_t *ipr = xc->regs.ipr;
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if (!xc->misspeculating()) {
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ipr[AlphaISA::IPR_ITB_TAG] = pc;
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ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
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ipr[AlphaISA::IPR_IVPTBR] | (VA_VPN(pc) << 3);
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}
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}
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Fault
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AlphaITB::translate(MemReqPtr &req) const
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{
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InternalProcReg *ipr = req->xc->regs.ipr;
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if (PC_PAL(req->vaddr)) {
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// strip off PAL PC marker (lsb is 1)
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req->paddr = (req->vaddr & ~3) & PA_IMPL_MASK;
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hits++;
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return No_Fault;
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}
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if (req->flags & PHYSICAL) {
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req->paddr = req->vaddr;
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} else {
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// verify that this is a good virtual address
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if (!validVirtualAddress(req->vaddr)) {
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fault(req->vaddr, req->xc);
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acv++;
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return ITB_Acv_Fault;
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}
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
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// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
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if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
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// only valid in kernel mode
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if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
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fault(req->vaddr, req->xc);
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acv++;
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return ITB_Acv_Fault;
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}
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req->paddr = req->vaddr & PA_IMPL_MASK;
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// sign extend the physical address properly
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if (req->paddr & PA_UNCACHED_BIT_40)
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req->paddr |= ULL(0xf0000000000);
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else
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req->paddr &= ULL(0xffffffffff);
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} else {
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// not a physical address: need to look up pte
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AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
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DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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if (!pte) {
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fault(req->vaddr, req->xc);
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misses++;
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return ITB_Fault_Fault;
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}
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req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3);
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// check permissions for this access
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if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
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// instruction access fault
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fault(req->vaddr, req->xc);
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acv++;
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return ITB_Acv_Fault;
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}
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hits++;
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}
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}
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// check that the physical address is ok (catch bad physical addresses)
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if (req->paddr & ~PA_IMPL_MASK)
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return Machine_Check_Fault;
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checkCacheability(req);
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return No_Fault;
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha DTB
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//
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AlphaDTB::AlphaDTB(const std::string &name, int size)
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: AlphaTLB(name, size)
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{}
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void
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AlphaDTB::regStats()
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{
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read_hits
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.name(name() + ".read_hits")
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.desc("DTB read hits")
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;
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read_misses
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.name(name() + ".read_misses")
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.desc("DTB read misses")
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;
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read_acv
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.name(name() + ".read_acv")
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.desc("DTB read access violations")
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;
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read_accesses
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.name(name() + ".read_accesses")
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.desc("DTB read accesses")
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;
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write_hits
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.name(name() + ".write_hits")
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.desc("DTB write hits")
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;
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write_misses
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.name(name() + ".write_misses")
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.desc("DTB write misses")
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;
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write_acv
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.name(name() + ".write_acv")
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.desc("DTB write access violations")
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;
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write_accesses
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.name(name() + ".write_accesses")
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.desc("DTB write accesses")
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;
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hits
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.name(name() + ".hits")
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.desc("DTB hits")
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;
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misses
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.name(name() + ".misses")
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.desc("DTB misses")
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;
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acv
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.name(name() + ".acv")
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.desc("DTB access violations")
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;
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accesses
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.name(name() + ".accesses")
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.desc("DTB accesses")
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;
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|
hits = read_hits + write_hits;
|
|
misses = read_misses + write_misses;
|
|
acv = read_acv + write_acv;
|
|
accesses = read_accesses + write_accesses;
|
|
}
|
|
|
|
void
|
|
AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
|
|
{
|
|
uint64_t *ipr = xc->regs.ipr;
|
|
|
|
// set fault address and flags
|
|
if (!xc->misspeculating() && !xc->regs.intrlock) {
|
|
// set VA register with faulting address
|
|
ipr[AlphaISA::IPR_VA] = vaddr;
|
|
|
|
// set MM_STAT register flags
|
|
ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11)
|
|
| ((RA(xc->getInst()) & 0x1f) << 6)
|
|
| (flags & 0x3f));
|
|
|
|
// set VA_FORM register with faulting formatted address
|
|
ipr[AlphaISA::IPR_VA_FORM] =
|
|
ipr[AlphaISA::IPR_MVPTBR] | (VA_VPN(vaddr) << 3);
|
|
|
|
// lock these registers until the VA register is read
|
|
xc->regs.intrlock = true;
|
|
}
|
|
}
|
|
|
|
Fault
|
|
AlphaDTB::translate(MemReqPtr &req, bool write) const
|
|
{
|
|
RegFile *regs = &req->xc->regs;
|
|
Addr pc = regs->pc;
|
|
InternalProcReg *ipr = regs->ipr;
|
|
|
|
AlphaISA::mode_type mode =
|
|
(AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
|
|
|
|
if (PC_PAL(pc)) {
|
|
mode = (req->flags & ALTMODE) ?
|
|
(AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
|
|
: AlphaISA::mode_kernel;
|
|
}
|
|
|
|
if (req->flags & PHYSICAL) {
|
|
req->paddr = req->vaddr;
|
|
} else {
|
|
// verify that this is a good virtual address
|
|
if (!validVirtualAddress(req->vaddr)) {
|
|
fault(req->vaddr,
|
|
((write ? MM_STAT_WR_MASK : 0) | MM_STAT_BAD_VA_MASK |
|
|
MM_STAT_ACV_MASK),
|
|
req->xc);
|
|
|
|
if (write) { write_acv++; } else { read_acv++; }
|
|
return DTB_Fault_Fault;
|
|
}
|
|
|
|
// Check for "superpage" mapping
|
|
if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
|
|
|
|
// only valid in kernel mode
|
|
if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
|
|
AlphaISA::mode_kernel) {
|
|
fault(req->vaddr,
|
|
((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK),
|
|
req->xc);
|
|
if (write) { write_acv++; } else { read_acv++; }
|
|
return DTB_Acv_Fault;
|
|
}
|
|
|
|
req->paddr = req->vaddr & PA_IMPL_MASK;
|
|
|
|
// sign extend the physical address properly
|
|
if (req->paddr & PA_UNCACHED_BIT_40)
|
|
req->paddr |= ULL(0xf0000000000);
|
|
else
|
|
req->paddr &= ULL(0xffffffffff);
|
|
|
|
} else {
|
|
if (write)
|
|
write_accesses++;
|
|
else
|
|
read_accesses++;
|
|
|
|
// not a physical address: need to look up pte
|
|
AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
|
|
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
|
|
|
if (!pte) {
|
|
// page fault
|
|
fault(req->vaddr,
|
|
((write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK),
|
|
req->xc);
|
|
if (write) { write_misses++; } else { read_misses++; }
|
|
return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault;
|
|
}
|
|
|
|
req->paddr = PA_PFN2PA(pte->ppn) | VA_POFS(req->vaddr);
|
|
|
|
if (write) {
|
|
if (!(pte->xwe & MODE2MASK(mode))) {
|
|
// declare the instruction access fault
|
|
fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_ACV_MASK |
|
|
(pte->fonw ? MM_STAT_FONW_MASK : 0),
|
|
req->xc);
|
|
write_acv++;
|
|
return DTB_Fault_Fault;
|
|
}
|
|
if (pte->fonw) {
|
|
fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK,
|
|
req->xc);
|
|
write_acv++;
|
|
return DTB_Fault_Fault;
|
|
}
|
|
} else {
|
|
if (!(pte->xre & MODE2MASK(mode))) {
|
|
fault(req->vaddr,
|
|
MM_STAT_ACV_MASK |
|
|
(pte->fonr ? MM_STAT_FONR_MASK : 0),
|
|
req->xc);
|
|
read_acv++;
|
|
return DTB_Acv_Fault;
|
|
}
|
|
if (pte->fonr) {
|
|
fault(req->vaddr, MM_STAT_FONR_MASK, req->xc);
|
|
read_acv++;
|
|
return DTB_Fault_Fault;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (write)
|
|
write_hits++;
|
|
else
|
|
read_hits++;
|
|
}
|
|
|
|
// check that the physical address is ok (catch bad physical addresses)
|
|
if (req->paddr & ~PA_IMPL_MASK)
|
|
return Machine_Check_Fault;
|
|
|
|
checkCacheability(req);
|
|
|
|
return No_Fault;
|
|
}
|
|
|
|
AlphaISA::PTE &
|
|
AlphaTLB::index(bool advance)
|
|
{
|
|
AlphaISA::PTE *pte = &table[nlu];
|
|
|
|
if (advance)
|
|
nextnlu();
|
|
|
|
return *pte;
|
|
}
|
|
|
|
DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
Param<int> size;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
INIT_PARAM_DFLT(size, "TLB size", 48)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
|
|
CREATE_SIM_OBJECT(AlphaITB)
|
|
{
|
|
return new AlphaITB(getInstanceName(), size);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
Param<int> size;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
INIT_PARAM_DFLT(size, "TLB size", 64)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
|
|
CREATE_SIM_OBJECT(AlphaDTB)
|
|
{
|
|
return new AlphaDTB(getInstanceName(), size);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
|
|
|