dc8018a5c3
Result of running 'hg m5style --skip-all --fix-white -a'.
101 lines
3.5 KiB
C++
101 lines
3.5 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __MEM_MPORT_HH__
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#define __MEM_MPORT_HH__
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#include "mem/mem_object.hh"
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#include "mem/tport.hh"
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/*
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* This file defines a port class which is used for sending and receiving
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* messages. These messages are atomic units which don't interact and
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* should be smaller than a cache block. This class is based on
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* the underpinnings of SimpleTimingPort, but it tweaks some of the external
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* functions.
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*/
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class MessageSlavePort : public SimpleTimingPort
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{
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public:
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MessageSlavePort(const std::string &name, MemObject *owner) :
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SimpleTimingPort(name, owner)
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{}
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virtual ~MessageSlavePort()
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{}
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protected:
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Tick recvAtomic(PacketPtr pkt);
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virtual Tick recvMessage(PacketPtr pkt) = 0;
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};
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class MessageMasterPort : public QueuedMasterPort
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{
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public:
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MessageMasterPort(const std::string &name, MemObject *owner) :
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QueuedMasterPort(name, owner, reqQueue, snoopRespQueue),
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reqQueue(*owner, *this), snoopRespQueue(*owner, *this)
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{}
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virtual ~MessageMasterPort()
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{}
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bool recvTimingResp(PacketPtr pkt) { recvResponse(pkt); return true; }
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protected:
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/** A packet queue for outgoing packets. */
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ReqPacketQueue reqQueue;
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SnoopRespPacketQueue snoopRespQueue;
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// Accept and ignore responses.
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virtual Tick recvResponse(PacketPtr pkt)
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{
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return 0;
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}
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};
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#endif
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