32509d8387
arch/alpha/ev5.cc:
Fix up some stuff I missed in the last kernel stats checkin.
cpu/checker/cpu.cc:
Allow the checker to disable its kernel stats.
cpu/cpu_exec_context.cc:
Allow CPUExecContext to be created without kernelStats.
cpu/cpu_exec_context.hh:
Allow CPUExecContext to be created without kernelStats. Default usage leaves kernelStats on.
--HG--
extra : convert_revision : 8ed5bffd3a5b6275baa07fb4ea385eeab1a0456a
524 lines
14 KiB
C++
524 lines
14 KiB
C++
/*
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* Copyright (c) 2001-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_CPU_EXEC_CONTEXT_HH__
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#define __CPU_CPU_EXEC_CONTEXT_HH__
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#include "arch/isa_traits.hh"
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#include "config/full_system.hh"
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#include "cpu/exec_context.hh"
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#include "mem/functional/functional.hh"
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#include "mem/mem_req.hh"
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#include "sim/byteswap.hh"
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#include "sim/eventq.hh"
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#include "sim/host.hh"
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#include "sim/serialize.hh"
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// forward declaration: see functional_memory.hh
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class FunctionalMemory;
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class PhysicalMemory;
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class BaseCPU;
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#if FULL_SYSTEM
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#include "sim/system.hh"
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#include "arch/tlb.hh"
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class FunctionProfile;
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class ProfileNode;
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class MemoryController;
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namespace Kernel {
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class Statistics;
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};
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#else // !FULL_SYSTEM
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#include "sim/process.hh"
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#endif // FULL_SYSTEM
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//
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// The CPUExecContext object represents a functional context for
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// instruction execution. It incorporates everything required for
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// architecture-level functional simulation of a single thread.
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//
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class CPUExecContext
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{
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protected:
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscRegFile MiscRegFile;
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typedef TheISA::MiscReg MiscReg;
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public:
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typedef ExecContext::Status Status;
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private:
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Status _status;
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public:
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Status status() const { return _status; }
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void setStatus(Status newStatus) { _status = newStatus; }
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1);
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/// Set the status to Suspended.
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void suspend();
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/// Set the status to Unallocated.
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void deallocate();
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/// Set the status to Halted.
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void halt();
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protected:
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RegFile regs; // correct-path register context
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public:
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// pointer to CPU associated with this context
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BaseCPU *cpu;
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ProxyExecContext<CPUExecContext> *proxy;
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// Current instruction
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MachInst inst;
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// Index of hardware thread context on the CPU that this represents.
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int thread_num;
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// ID of this context w.r.t. the System or Process object to which
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// it belongs. For full-system mode, this is the system CPU ID.
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int cpu_id;
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Tick lastActivate;
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Tick lastSuspend;
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#if FULL_SYSTEM
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FunctionalMemory *mem;
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AlphaITB *itb;
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AlphaDTB *dtb;
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System *system;
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// the following two fields are redundant, since we can always
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// look them up through the system pointer, but we'll leave them
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// here for now for convenience
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MemoryController *memctrl;
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PhysicalMemory *physmem;
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FunctionProfile *profile;
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ProfileNode *profileNode;
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Addr profilePC;
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void dumpFuncProfile();
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EndQuiesceEvent *quiesceEvent;
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EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
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Tick readLastActivate() { return lastActivate; }
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Tick readLastSuspend() { return lastSuspend; }
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void profileClear();
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void profileSample();
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Kernel::Statistics *getKernelStats() { return kernelStats; }
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Kernel::Statistics *kernelStats;
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#else
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Process *process;
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FunctionalMemory *mem; // functional storage for process address space
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// Address space ID. Note that this is used for TIMING cache
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// simulation only; all functional memory accesses should use
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// one of the FunctionalMemory pointers above.
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short asid;
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#endif
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/**
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* Temporary storage to pass the source address from copy_load to
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* copy_store.
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* @todo Remove this temporary when we have a better way to do it.
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*/
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Addr copySrcAddr;
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/**
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* Temp storage for the physical source address of a copy.
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* @todo Remove this temporary when we have a better way to do it.
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*/
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Addr copySrcPhysAddr;
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/*
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* number of executed instructions, for matching with syscall trace
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* points in EIO files.
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*/
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Counter func_exe_inst;
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//
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// Count failed store conditionals so we can warn of apparent
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// application deadlock situations.
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unsigned storeCondFailures;
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// constructor: initialize context from given process structure
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#if FULL_SYSTEM
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CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
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AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_mem,
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bool use_kernel_stats = true);
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#else
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CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
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CPUExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
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int _asid);
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// Constructor to use XC to pass reg file around. Not used for anything
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// else.
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CPUExecContext(RegFile *regFile);
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#endif
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virtual ~CPUExecContext();
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virtual void takeOverFrom(ExecContext *oldContext);
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void regStats(const std::string &name);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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BaseCPU *getCpuPtr() { return cpu; }
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ExecContext *getProxy() { return proxy; }
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int getThreadNum() { return thread_num; }
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#if FULL_SYSTEM
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System *getSystemPtr() { return system; }
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PhysicalMemory *getPhysMemPtr() { return physmem; }
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AlphaITB *getITBPtr() { return itb; }
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AlphaDTB *getDTBPtr() { return dtb; }
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bool validInstAddr(Addr addr) { return true; }
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bool validDataAddr(Addr addr) { return true; }
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int getInstAsid() { return regs.instAsid(); }
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int getDataAsid() { return regs.dataAsid(); }
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Fault translateInstReq(MemReqPtr &req)
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{
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return itb->translate(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dtb->translate(req, false);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dtb->translate(req, true);
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}
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#else
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Process *getProcessPtr() { return process; }
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bool validInstAddr(Addr addr)
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{ return process->validInstAddr(addr); }
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bool validDataAddr(Addr addr)
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{ return process->validDataAddr(addr); }
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int getInstAsid() { return asid; }
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int getDataAsid() { return asid; }
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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Fault translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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#endif
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template <class T>
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Fault read(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->flags & LOCKED) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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Fault error;
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error = mem->read(req, data);
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data = LittleEndianGuest::gtoh(data);
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return error;
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}
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template <class T>
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Fault write(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->flags & LOCKED) {
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xc = req->xc;
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if (req->flags & UNCACHEABLE) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < system->execContexts.size(); i++){
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xc = system->execContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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return mem->write(req, (T)LittleEndianGuest::htog(data));
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}
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virtual bool misspeculating();
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MachInst getInst() { return inst; }
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void setInst(MachInst new_inst)
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{
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inst = new_inst;
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}
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Fault instRead(MemReqPtr &req)
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{
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return mem->read(req, inst);
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}
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void setCpuId(int id) { cpu_id = id; }
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int readCpuId() { return cpu_id; }
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FunctionalMemory *getMemPtr() { return mem; }
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void copyArchRegs(ExecContext *xc);
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{
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return regs.intRegFile[reg_idx];
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}
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float readFloatRegSingle(int reg_idx)
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{
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return (float)regs.floatRegFile.d[reg_idx];
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}
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double readFloatRegDouble(int reg_idx)
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{
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return regs.floatRegFile.d[reg_idx];
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}
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uint64_t readFloatRegInt(int reg_idx)
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{
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return regs.floatRegFile.q[reg_idx];
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}
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void setIntReg(int reg_idx, uint64_t val)
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{
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regs.intRegFile[reg_idx] = val;
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}
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void setFloatRegSingle(int reg_idx, float val)
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{
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regs.floatRegFile.d[reg_idx] = (double)val;
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}
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void setFloatRegDouble(int reg_idx, double val)
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{
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regs.floatRegFile.d[reg_idx] = val;
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}
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void setFloatRegInt(int reg_idx, uint64_t val)
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{
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regs.floatRegFile.q[reg_idx] = val;
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}
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uint64_t readPC()
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{
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return regs.pc;
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}
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void setPC(uint64_t val)
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{
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regs.pc = val;
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}
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uint64_t readNextPC()
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{
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return regs.npc;
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}
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void setNextPC(uint64_t val)
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{
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regs.npc = val;
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}
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uint64_t readNextNPC()
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{
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return regs.nnpc;
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}
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void setNextNPC(uint64_t val)
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{
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regs.nnpc = val;
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}
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MiscReg readMiscReg(int misc_reg)
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{
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return regs.miscRegs.readReg(misc_reg);
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}
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
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{
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return regs.miscRegs.readRegWithEffect(misc_reg, fault, proxy);
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}
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Fault setMiscReg(int misc_reg, const MiscReg &val)
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{
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return regs.miscRegs.setReg(misc_reg, val);
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}
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
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{
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return regs.miscRegs.setRegWithEffect(misc_reg, val, proxy);
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}
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unsigned readStCondFailures() { return storeCondFailures; }
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void setStCondFailures(unsigned sc_failures)
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{ storeCondFailures = sc_failures; }
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void clearArchRegs() { memset(®s, 0, sizeof(regs)); }
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#if FULL_SYSTEM
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int readIntrFlag() { return regs.intrflag; }
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void setIntrFlag(int val) { regs.intrflag = val; }
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Fault hwrei();
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bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
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bool simPalCheck(int palFunc);
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#endif
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#if !FULL_SYSTEM
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TheISA::IntReg getSyscallArg(int i)
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{
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return regs.intRegFile[TheISA::ArgumentReg0 + i];
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}
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// used to shift args for indirect syscall
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void setSyscallArg(int i, TheISA::IntReg val)
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{
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regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
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}
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void setSyscallReturn(SyscallReturn return_value)
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{
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TheISA::setSyscallReturn(return_value, ®s);
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}
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void syscall()
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{
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process->syscall(proxy);
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}
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Counter readFuncExeInst() { return func_exe_inst; }
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void setFuncExeInst(Counter new_val) { func_exe_inst = new_val; }
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#endif
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};
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// for non-speculative execution context, spec_mode is always false
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inline bool
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CPUExecContext::misspeculating()
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{
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return false;
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}
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#endif // __CPU_CPU_EXEC_CONTEXT_HH__
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