c9ad4a15d6
cpu/checker/cpu.cc: Cleanup checker, give more useful warning messages. Also fix bug cpu/checker/cpu.hh: Cleanup checker, use forward declaration instead of include. --HG-- extra : convert_revision : 8f231199a0a75788218320cdbcc7f70441e5d574
326 lines
8.9 KiB
C++
326 lines
8.9 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_CHECKER_CPU_HH__
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#define __CPU_CHECKER_CPU_HH__
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#include <list>
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#include <queue>
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#include <map>
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/static_inst.hh"
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#include "sim/eventq.hh"
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// forward declarations
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#if FULL_SYSTEM
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class Processor;
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class AlphaITB;
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class AlphaDTB;
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class PhysicalMemory;
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class RemoteGDB;
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class GDBListener;
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#else
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class Process;
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#endif // FULL_SYSTEM
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template <class>
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class BaseDynInst;
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class ExecContext;
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class MemInterface;
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class Checkpoint;
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class Sampler;
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class CheckerCPU : public BaseCPU
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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public:
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// main simulation loop (one cycle)
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virtual void init();
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struct Params : public BaseCPU::Params
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{
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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FunctionalMemory *mem;
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#else
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Process *process;
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#endif
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bool exitOnError;
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};
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public:
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CheckerCPU(Params *p);
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virtual ~CheckerCPU();
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void setMemory(FunctionalMemory *mem);
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FunctionalMemory *memPtr;
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#if FULL_SYSTEM
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void setSystem(System *system);
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System *systemPtr;
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#endif
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public:
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// execution context
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CPUExecContext *cpuXC;
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ExecContext *xcProxy;
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AlphaITB *itb;
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AlphaDTB *dtb;
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#if FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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#endif
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union Result {
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uint64_t integer;
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float fp;
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double dbl;
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};
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Result result;
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// current instruction
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MachInst machInst;
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// Refcounted pointer to the one memory request.
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MemReqPtr memReq;
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StaticInstPtr curStaticInst;
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// number of simulated instructions
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Counter numInst;
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Counter startNumInst;
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std::queue<int> miscRegIdxs;
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
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// These functions are only used in CPU models that split
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// effective address computation from the actual memory access.
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void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
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Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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}
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void writeHint(Addr addr, int size, unsigned flags)
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{
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// need to do this...
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}
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntReg(const StaticInst *si, int idx)
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{
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return cpuXC->readIntReg(si->srcRegIdx(idx));
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}
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float readFloatRegSingle(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return cpuXC->readFloatRegSingle(reg_idx);
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}
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double readFloatRegDouble(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return cpuXC->readFloatRegDouble(reg_idx);
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}
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uint64_t readFloatRegInt(const StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return cpuXC->readFloatRegInt(reg_idx);
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}
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void setIntReg(const StaticInst *si, int idx, uint64_t val)
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{
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cpuXC->setIntReg(si->destRegIdx(idx), val);
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result.integer = val;
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}
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void setFloatRegSingle(const StaticInst *si, int idx, float val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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cpuXC->setFloatRegSingle(reg_idx, val);
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result.fp = val;
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}
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void setFloatRegDouble(const StaticInst *si, int idx, double val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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cpuXC->setFloatRegDouble(reg_idx, val);
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result.dbl = val;
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}
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void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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cpuXC->setFloatRegInt(reg_idx, val);
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result.integer = val;
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}
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uint64_t readPC() { return cpuXC->readPC(); }
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void setNextPC(uint64_t val) {
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cpuXC->setNextPC(val);
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}
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MiscReg readMiscReg(int misc_reg)
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{
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return cpuXC->readMiscReg(misc_reg);
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}
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
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{
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return cpuXC->readMiscRegWithEffect(misc_reg, fault);
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}
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Fault setMiscReg(int misc_reg, const MiscReg &val)
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{
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result.integer = val;
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miscRegIdxs.push(misc_reg);
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return cpuXC->setMiscReg(misc_reg, val);
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}
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
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{
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miscRegIdxs.push(misc_reg);
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return cpuXC->setMiscRegWithEffect(misc_reg, val);
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}
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void recordPCChange(uint64_t val) { changedPC = true; }
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void recordNextPCChange(uint64_t val) { changedNextPC = true; }
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bool translateInstReq(MemReqPtr &req);
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void translateDataWriteReq(MemReqPtr &req);
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void translateDataReadReq(MemReqPtr &req);
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#if FULL_SYSTEM
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Fault hwrei() { return cpuXC->hwrei(); }
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int readIntrFlag() { return cpuXC->readIntrFlag(); }
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void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
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bool inPalMode() { return cpuXC->inPalMode(); }
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void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
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bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
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#else
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// Assume that the normal CPU's call to syscall was successful.
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// The checker's state would have already been updated by the syscall.
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void syscall() { }
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#endif
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void handleError()
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{
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if (exitOnError)
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panic("Checker found error!");
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}
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bool checkFlags(MemReqPtr &req);
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ExecContext *xcBase() { return xcProxy; }
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CPUExecContext *cpuXCBase() { return cpuXC; }
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Result unverifiedResult;
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MemReqPtr unverifiedReq;
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bool changedPC;
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bool willChangePC;
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uint64_t newPC;
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bool changedNextPC;
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bool exitOnError;
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InstSeqNum youngestSN;
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};
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template <class DynInstPtr>
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class Checker : public CheckerCPU
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{
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public:
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Checker(Params *p)
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: CheckerCPU(p)
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{ }
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void switchOut(Sampler *s);
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void takeOverFrom(BaseCPU *oldCPU);
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void tick(DynInstPtr &inst);
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void validateInst(DynInstPtr &inst);
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void validateExecution(DynInstPtr &inst);
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void validateState();
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std::list<DynInstPtr> instList;
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typedef typename std::list<DynInstPtr>::iterator InstListIt;
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void dumpInsts();
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};
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#endif // __CPU_CHECKER_CPU_HH__
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