gem5/ext/sst/ExtSlave.hh
Curtis Dunham f05cb84ed1 ext: Add SST connector
This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
2015-04-08 15:56:06 -05:00

119 lines
3.8 KiB
C++

// Copyright (c) 2015 ARM Limited
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// Copyright 2009-2014 Sandia Coporation. Under the terms
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#ifndef EXT_SST_EXTSLAVE_HH
#define EXT_SST_EXTSLAVE_HH
#include <sst/core/serialization.h>
#include <sst/core/component.h>
#include <sst/core/output.h>
#include <sst/core/interfaces/simpleMem.h>
#include <sim/sim_object.hh>
#include <mem/packet.hh>
#include <mem/request.hh>
#include <mem/external_slave.hh>
namespace SST {
class Link;
class Event;
class MemEvent;
namespace gem5 {
class gem5Component;
class ExtSlave : public ExternalSlave::Port {
public:
const std::string name;
bool
recvTimingSnoopResp(PacketPtr packet)
{
fatal("recvTimingSnoopResp unimplemented");
return false;
}
bool recvTimingReq(PacketPtr packet);
void recvFunctional(PacketPtr packet);
void recvRespRetry();
Tick
recvAtomic(PacketPtr packet)
{
fatal("recvAtomic unimplemented");
}
enum Phase { CONSTRUCTION, INIT, RUN };
gem5Component *comp;
Output &out;
Phase simPhase;
std::list<MemEvent*>* initPackets;
Link* link;
std::list<PacketPtr> respQ;
bool blocked() { return !respQ.empty(); }
typedef std::map<Event::id_type, ::Packet*> PacketMap_t;
PacketMap_t PacketMap; // SST Event id -> gem5 Packet*
public:
ExtSlave(gem5Component*, Output&, ExternalSlave&, std::string&);
void init(unsigned phase);
void
setup()
{
simPhase = RUN;
}
void handleEvent(Event*);
};
}
}
#endif