This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object.
404 lines
11 KiB
C++
404 lines
11 KiB
C++
/*
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* Copyright (c) 2001-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#ifndef __CPU_SIMPLE_THREAD_HH__
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#define __CPU_SIMPLE_THREAD_HH__
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#include "arch/isa.hh"
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#include "arch/isa_traits.hh"
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#include "arch/registers.hh"
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#include "arch/tlb.hh"
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#include "arch/types.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "cpu/decode.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_state.hh"
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#include "debug/FloatRegs.hh"
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#include "debug/IntRegs.hh"
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#include "mem/request.hh"
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#include "sim/byteswap.hh"
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#include "sim/eventq.hh"
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#include "sim/serialize.hh"
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class BaseCPU;
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#if FULL_SYSTEM
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#include "sim/system.hh"
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class FunctionProfile;
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class ProfileNode;
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class FunctionalPort;
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class PhysicalPort;
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namespace TheISA {
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namespace Kernel {
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class Statistics;
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};
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};
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#else // !FULL_SYSTEM
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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class TranslatingPort;
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#endif // FULL_SYSTEM
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/**
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* The SimpleThread object provides a combination of the ThreadState
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* object and the ThreadContext interface. It implements the
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* ThreadContext interface so that a ProxyThreadContext class can be
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* made using SimpleThread as the template parameter (see
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* thread_context.hh). It adds to the ThreadState object by adding all
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* the objects needed for simple functional execution, including a
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* simple architectural register file, and pointers to the ITB and DTB
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* in full system mode. For CPU models that do not need more advanced
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* ways to hold state (i.e. a separate physical register file, or
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* separate fetch and commit PC's), this SimpleThread class provides
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* all the necessary state for full architecture-level functional
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* simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
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* examples.
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*/
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class SimpleThread : public ThreadState
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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public:
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typedef ThreadContext::Status Status;
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protected:
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union {
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FloatReg f[TheISA::NumFloatRegs];
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FloatRegBits i[TheISA::NumFloatRegs];
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} floatRegs;
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TheISA::IntReg intRegs[TheISA::NumIntRegs];
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TheISA::ISA isa; // one "instance" of the current ISA.
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TheISA::PCState _pcState;
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/** Did this instruction execute or is it predicated false */
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bool predicate;
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public:
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std::string name() const
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{
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return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId());
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}
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// pointer to CPU associated with this SimpleThread
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BaseCPU *cpu;
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ProxyThreadContext<SimpleThread> *tc;
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System *system;
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TheISA::TLB *itb;
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TheISA::TLB *dtb;
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Decoder decoder;
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// constructor: initialize SimpleThread from given process structure
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#if FULL_SYSTEM
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SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
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TheISA::TLB *_itb, TheISA::TLB *_dtb,
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bool use_kernel_stats = true);
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#else
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SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
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TheISA::TLB *_itb, TheISA::TLB *_dtb);
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#endif
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SimpleThread();
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virtual ~SimpleThread();
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virtual void takeOverFrom(ThreadContext *oldContext);
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void regStats(const std::string &name);
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void copyTC(ThreadContext *context);
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void copyState(ThreadContext *oldContext);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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/***************************************************************
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* SimpleThread functions to provide CPU with access to various
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* state.
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**************************************************************/
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/** Returns the pointer to this SimpleThread's ThreadContext. Used
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* when a ThreadContext must be passed to objects outside of the
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* CPU.
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*/
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ThreadContext *getTC() { return tc; }
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void demapPage(Addr vaddr, uint64_t asn)
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{
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itb->demapPage(vaddr, asn);
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dtb->demapPage(vaddr, asn);
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}
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void demapInstPage(Addr vaddr, uint64_t asn)
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{
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itb->demapPage(vaddr, asn);
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}
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void demapDataPage(Addr vaddr, uint64_t asn)
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{
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dtb->demapPage(vaddr, asn);
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}
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#if FULL_SYSTEM
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void dumpFuncProfile();
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Fault hwrei();
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bool simPalCheck(int palFunc);
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#endif
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/*******************************************
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* ThreadContext interface functions.
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******************************************/
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BaseCPU *getCpuPtr() { return cpu; }
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TheISA::TLB *getITBPtr() { return itb; }
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TheISA::TLB *getDTBPtr() { return dtb; }
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Decoder *getDecoderPtr() { return &decoder; }
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System *getSystemPtr() { return system; }
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#if FULL_SYSTEM
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FunctionalPort *getPhysPort() { return physPort; }
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/** Return a virtual port. This port cannot be cached locally in an object.
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* After a CPU switch it may point to the wrong memory object which could
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* mean stale data.
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*/
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VirtualPort *getVirtPort() { return virtPort; }
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#endif
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Status status() const { return _status; }
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void setStatus(Status newStatus) { _status = newStatus; }
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1);
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/// Set the status to Suspended.
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void suspend();
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/// Set the status to Halted.
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void halt();
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virtual bool misspeculating();
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void copyArchRegs(ThreadContext *tc);
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void clearArchRegs()
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{
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_pcState = 0;
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memset(intRegs, 0, sizeof(intRegs));
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memset(floatRegs.i, 0, sizeof(floatRegs.i));
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isa.clear();
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}
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{
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int flatIndex = isa.flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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uint64_t regVal = intRegs[flatIndex];
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DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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}
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FloatReg readFloatReg(int reg_idx)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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FloatReg regVal = floatRegs.f[flatIndex];
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DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
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reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
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return regVal;
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}
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FloatRegBits readFloatRegBits(int reg_idx)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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FloatRegBits regVal = floatRegs.i[flatIndex];
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DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
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reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
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return regVal;
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}
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void setIntReg(int reg_idx, uint64_t val)
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{
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int flatIndex = isa.flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
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reg_idx, flatIndex, val);
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intRegs[flatIndex] = val;
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}
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void setFloatReg(int reg_idx, FloatReg val)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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floatRegs.f[flatIndex] = val;
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DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
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reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
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}
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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{
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int flatIndex = isa.flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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floatRegs.i[flatIndex] = val;
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DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
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reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
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}
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TheISA::PCState
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pcState()
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{
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return _pcState;
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}
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void
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pcState(const TheISA::PCState &val)
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{
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_pcState = val;
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}
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Addr
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instAddr()
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{
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return _pcState.instAddr();
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}
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Addr
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nextInstAddr()
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{
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return _pcState.nextInstAddr();
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}
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MicroPC
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microPC()
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{
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return _pcState.microPC();
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}
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bool readPredicate()
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{
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return predicate;
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}
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void setPredicate(bool val)
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{
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predicate = val;
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}
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MiscReg
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readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
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{
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return isa.readMiscRegNoEffect(misc_reg);
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}
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MiscReg
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readMiscReg(int misc_reg, ThreadID tid = 0)
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{
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return isa.readMiscReg(misc_reg, tc);
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}
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void
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setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
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{
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return isa.setMiscRegNoEffect(misc_reg, val);
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}
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void
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setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
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{
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return isa.setMiscReg(misc_reg, val, tc);
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}
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int
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flattenIntIndex(int reg)
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{
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return isa.flattenIntIndex(reg);
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}
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int
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flattenFloatIndex(int reg)
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{
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return isa.flattenFloatIndex(reg);
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}
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unsigned readStCondFailures() { return storeCondFailures; }
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void setStCondFailures(unsigned sc_failures)
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{ storeCondFailures = sc_failures; }
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#if !FULL_SYSTEM
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void syscall(int64_t callnum)
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{
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process->syscall(callnum, tc);
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}
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#endif
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};
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// for non-speculative execution context, spec_mode is always false
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inline bool
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SimpleThread::misspeculating()
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{
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return false;
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}
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#endif // __CPU_CPU_EXEC_CONTEXT_HH__
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