24da30e317
This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol.
119 lines
3.8 KiB
C++
119 lines
3.8 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*
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* Description: Perfect switch, of course it is perfect and no latency or what
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* so ever. Every cycle it is woke up and perform all the
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* necessary routings that must be done. Note, this switch also
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* has number of input ports/output ports and has a routing table
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* as well.
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*
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*/
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#ifndef PerfectSwitch_H
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#define PerfectSwitch_H
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#include "mem/ruby/common/Global.hh"
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#include "mem/gems_common/Vector.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/system/NodeID.hh"
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class MessageBuffer;
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class NetDest;
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class SimpleNetwork;
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class LinkOrder {
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public:
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int m_link;
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int m_value;
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};
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class PerfectSwitch : public Consumer {
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public:
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// Constructors
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// constructor specifying the number of ports
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PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr);
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void addInPort(const Vector<MessageBuffer*>& in);
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void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry);
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void clearRoutingTables();
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void clearBuffers();
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void reconfigureOutPort(const NetDest& routing_table_entry);
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int getInLinks() const { return m_in.size(); }
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int getOutLinks() const { return m_out.size(); }
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// Destructor
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~PerfectSwitch();
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// Public Methods
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void wakeup();
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void printStats(ostream& out) const;
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void clearStats();
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void printConfig(ostream& out) const;
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void print(ostream& out) const;
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private:
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// Private copy constructor and assignment operator
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PerfectSwitch(const PerfectSwitch& obj);
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PerfectSwitch& operator=(const PerfectSwitch& obj);
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// Data Members (m_ prefix)
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SwitchID m_switch_id;
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// vector of queues from the components
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Vector<Vector<MessageBuffer*> > m_in;
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Vector<Vector<MessageBuffer*> > m_out;
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Vector<NetDest> m_routing_table;
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Vector<LinkOrder> m_link_order;
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int m_virtual_networks;
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int m_round_robin_start;
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int m_wakeups_wo_switch;
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SimpleNetwork* m_network_ptr;
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};
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// Output operator declaration
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ostream& operator<<(ostream& out, const PerfectSwitch& obj);
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// ******************* Definitions *******************
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// Output operator definition
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extern inline
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ostream& operator<<(ostream& out, const PerfectSwitch& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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#endif //PerfectSwitch_H
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