2059 lines
67 KiB
Text
2059 lines
67 KiB
Text
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* AMD's contributions to the MOESI hammer protocol do not constitute an
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* endorsement of its similarity to any AMD products.
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*
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* Authors: Milo Martin
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* Brad Beckmann
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*/
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machine(L1Cache, "AMD Hammer-like protocol")
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: Sequencer * sequencer,
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CacheMemory * L1IcacheMemory,
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CacheMemory * L1DcacheMemory,
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CacheMemory * L2cacheMemory,
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int cache_response_latency = 10,
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int issue_latency = 2,
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int l2_cache_hit_latency = 10,
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bool no_mig_atomic = true,
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bool send_evictions
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{
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// NETWORK BUFFERS
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MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="false", vnet_type="request";
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MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="false", vnet_type="response";
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MessageBuffer unblockFromCache, network="To", virtual_network="5", ordered="false", vnet_type="unblock";
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MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="false", vnet_type="forward";
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MessageBuffer responseToCache, network="From", virtual_network="4", ordered="false", vnet_type="response";
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// STATES
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state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
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// Base states
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I, AccessPermission:Invalid, desc="Idle";
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S, AccessPermission:Read_Only, desc="Shared";
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O, AccessPermission:Read_Only, desc="Owned";
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M, AccessPermission:Read_Only, desc="Modified (dirty)";
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MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
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// Base states, locked and ready to service the mandatory queue
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IR, AccessPermission:Invalid, desc="Idle";
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SR, AccessPermission:Read_Only, desc="Shared";
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OR, AccessPermission:Read_Only, desc="Owned";
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MR, AccessPermission:Read_Only, desc="Modified (dirty)";
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MMR, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
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// Transient States
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IM, AccessPermission:Busy, "IM", desc="Issued GetX";
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SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have a valid copy of the line";
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OM, AccessPermission:Read_Only, "OM", desc="Issued GetX, received data";
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ISM, AccessPermission:Read_Only, "ISM", desc="Issued GetX, received valid data, waiting for all acks";
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M_W, AccessPermission:Read_Only, "M^W", desc="Issued GetS, received exclusive data";
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MM_W, AccessPermission:Read_Write, "MM^W", desc="Issued GetX, received exclusive data";
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IS, AccessPermission:Busy, "IS", desc="Issued GetS";
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SS, AccessPermission:Read_Only, "SS", desc="Issued GetS, received data, waiting for all acks";
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OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
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MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
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II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack";
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IT, AccessPermission:Busy, "IT", desc="Invalid block transferring to L1";
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ST, AccessPermission:Busy, "ST", desc="S block transferring to L1";
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OT, AccessPermission:Busy, "OT", desc="O block transferring to L1";
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MT, AccessPermission:Busy, "MT", desc="M block transferring to L1";
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MMT, AccessPermission:Busy, "MMT", desc="MM block transferring to L0";
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//Transition States Related to Flushing
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MI_F, AccessPermission:Busy, "MI_F", desc="Issued PutX due to a Flush, waiting for ack";
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MM_F, AccessPermission:Busy, "MM_F", desc="Issued GETF due to a Flush, waiting for ack";
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IM_F, AccessPermission:Busy, "IM_F", desc="Issued GetX due to a Flush";
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ISM_F, AccessPermission:Read_Only, "ISM_F", desc="Issued GetX, received data, waiting for all acks";
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SM_F, AccessPermission:Read_Only, "SM_F", desc="Issued GetX, we still have an old copy of the line";
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OM_F, AccessPermission:Read_Only, "OM_F", desc="Issued GetX, received data";
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MM_WF, AccessPermission:Busy, "MM_WF", desc="Issued GetX, received exclusive data";
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}
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// EVENTS
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enumeration(Event, desc="Cache events") {
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Load, desc="Load request from the processor";
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Ifetch, desc="I-fetch request from the processor";
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Store, desc="Store request from the processor";
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L2_Replacement, desc="L2 Replacement";
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L1_to_L2, desc="L1 to L2 transfer";
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Trigger_L2_to_L1D, desc="Trigger L2 to L1-Data transfer";
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Trigger_L2_to_L1I, desc="Trigger L2 to L1-Instruction transfer";
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Complete_L2_to_L1, desc="L2 to L1 transfer completed";
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// Requests
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Other_GETX, desc="A GetX from another processor";
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Other_GETS, desc="A GetS from another processor";
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Merged_GETS, desc="A Merged GetS from another processor";
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Other_GETS_No_Mig, desc="A GetS from another processor";
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NC_DMA_GETS, desc="special GetS when only DMA exists";
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Invalidate, desc="Invalidate block";
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// Responses
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Ack, desc="Received an ack message";
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Shared_Ack, desc="Received an ack message, responder has a shared copy";
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Data, desc="Received a data message";
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Shared_Data, desc="Received a data message, responder has a shared copy";
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Exclusive_Data, desc="Received a data message, responder had an exclusive copy, they gave it to us";
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Writeback_Ack, desc="Writeback O.K. from directory";
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Writeback_Nack, desc="Writeback not O.K. from directory";
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// Triggers
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All_acks, desc="Received all required data and message acks";
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All_acks_no_sharers, desc="Received all acks and no other processor has a shared copy";
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// For Flush
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Flush_line, desc="flush the cache line from all caches";
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Block_Ack, desc="the directory is blocked and ready for the flush";
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}
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// TYPES
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// STRUCTURE DEFINITIONS
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MessageBuffer mandatoryQueue, ordered="false";
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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DataBlock DataBlk, desc="data for the block";
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bool FromL2, default="false", desc="block just moved from L2";
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bool AtomicAccessed, default="false", desc="block just moved from L2";
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}
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// TBE fields
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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int NumPendingMsgs, desc="Number of acks/data messages that this processor is waiting for";
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bool Sharers, desc="On a GetS, did we find any other sharers in the system";
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bool AppliedSilentAcks, default="false", desc="for full-bit dir, does the pending msg count reflect the silent acks";
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MachineID LastResponder, desc="last machine to send a response for this request";
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MachineID CurOwner, desc="current owner of the block, used for UnblockS responses";
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Time InitialRequestTime, default="0", desc="time the initial requests was sent from the L1Cache";
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Time ForwardRequestTime, default="0", desc="time the dir forwarded the request";
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Time FirstResponseTime, default="0", desc="the time the first response was received";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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TBETable TBEs, template_hack="<L1Cache_TBE>";
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void set_cache_entry(AbstractCacheEntry b);
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void unset_cache_entry();
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void set_tbe(TBE b);
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void unset_tbe();
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void wakeUpAllBuffers();
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void wakeUpBuffers(Address a);
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Entry getCacheEntry(Address address), return_by_pointer="yes" {
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Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address));
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if(is_valid(L2cache_entry)) {
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return L2cache_entry;
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}
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(address));
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if(is_valid(L1Dcache_entry)) {
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return L1Dcache_entry;
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}
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(address));
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return L1Icache_entry;
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}
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DataBlock getDataBlock(Address addr), return_by_ref="yes" {
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return getCacheEntry(addr).DataBlk;
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}
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Entry getL2CacheEntry(Address address), return_by_pointer="yes" {
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Entry L2cache_entry := static_cast(Entry, "pointer", L2cacheMemory.lookup(address));
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return L2cache_entry;
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}
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Entry getL1DCacheEntry(Address address), return_by_pointer="yes" {
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory.lookup(address));
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return L1Dcache_entry;
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}
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Entry getL1ICacheEntry(Address address), return_by_pointer="yes" {
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory.lookup(address));
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return L1Icache_entry;
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}
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State getState(TBE tbe, Entry cache_entry, Address addr) {
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if(is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
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assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
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assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
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assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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AccessPermission getAccessPermission(Address addr) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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return L1Cache_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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return L1Cache_State_to_permission(cache_entry.CacheState);
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}
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Entry cache_entry, Address addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(L1Cache_State_to_permission(state));
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}
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}
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Event mandatory_request_type_to_event(RubyRequestType type) {
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if (type == RubyRequestType:LD) {
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return Event:Load;
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} else if (type == RubyRequestType:IFETCH) {
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return Event:Ifetch;
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} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
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return Event:Store;
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} else if ((type == RubyRequestType:FLUSH)) {
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return Event:Flush_line;
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} else {
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error("Invalid RubyRequestType");
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}
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}
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GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
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if (machineIDToMachineType(sender) == MachineType:L1Cache) {
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//
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// NOTE direct local hits should not call this
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//
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return GenericMachineType:L1Cache_wCC;
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} else {
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return ConvertMachToGenericMach(machineIDToMachineType(sender));
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}
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}
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GenericMachineType testAndClearLocalHit(Entry cache_entry) {
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if (is_valid(cache_entry) && cache_entry.FromL2) {
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cache_entry.FromL2 := false;
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return GenericMachineType:L2Cache;
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} else {
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return GenericMachineType:L1Cache;
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}
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}
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bool IsAtomicAccessed(Entry cache_entry) {
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assert(is_valid(cache_entry));
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return cache_entry.AtomicAccessed;
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}
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MessageBuffer triggerQueue, ordered="false";
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// ** OUT_PORTS **
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out_port(requestNetwork_out, RequestMsg, requestFromCache);
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out_port(responseNetwork_out, ResponseMsg, responseFromCache);
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out_port(unblockNetwork_out, ResponseMsg, unblockFromCache);
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out_port(triggerQueue_out, TriggerMsg, triggerQueue);
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// ** IN_PORTS **
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// Trigger Queue
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in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
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if (triggerQueue_in.isReady()) {
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peek(triggerQueue_in, TriggerMsg) {
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := TBEs[in_msg.Address];
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if (in_msg.Type == TriggerType:L2_to_L1) {
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trigger(Event:Complete_L2_to_L1, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == TriggerType:ALL_ACKS) {
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trigger(Event:All_acks, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == TriggerType:ALL_ACKS_NO_SHARERS) {
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trigger(Event:All_acks_no_sharers, in_msg.Address, cache_entry, tbe);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Nothing from the unblock network
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// Response Network
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in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) {
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if (responseToCache_in.isReady()) {
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peek(responseToCache_in, ResponseMsg, block_on="Address") {
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := TBEs[in_msg.Address];
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if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
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trigger(Event:Shared_Ack, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:DATA) {
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trigger(Event:Data, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
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trigger(Event:Shared_Data, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
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trigger(Event:Exclusive_Data, in_msg.Address, cache_entry, tbe);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Forward Network
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in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) {
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if (forwardToCache_in.isReady()) {
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peek(forwardToCache_in, RequestMsg, block_on="Address") {
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := TBEs[in_msg.Address];
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if ((in_msg.Type == CoherenceRequestType:GETX) || (in_msg.Type == CoherenceRequestType:GETF)) {
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trigger(Event:Other_GETX, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
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trigger(Event:Merged_GETS, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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if (machineCount(MachineType:L1Cache) > 1) {
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if (is_valid(cache_entry)) {
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if (IsAtomicAccessed(cache_entry) && no_mig_atomic) {
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trigger(Event:Other_GETS_No_Mig, in_msg.Address, cache_entry, tbe);
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} else {
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trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
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}
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} else {
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trigger(Event:Other_GETS, in_msg.Address, cache_entry, tbe);
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}
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} else {
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trigger(Event:NC_DMA_GETS, in_msg.Address, cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceRequestType:INV) {
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trigger(Event:Invalidate, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
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trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
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trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:BLOCK_ACK) {
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trigger(Event:Block_Ack, in_msg.Address, cache_entry, tbe);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Nothing from the request network
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// Mandatory Queue
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in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) {
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if (mandatoryQueue_in.isReady()) {
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peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
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// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
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TBE tbe := TBEs[in_msg.LineAddress];
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if (in_msg.Type == RubyRequestType:IFETCH) {
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// ** INSTRUCTION ACCESS ***
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Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
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if (is_valid(L1Icache_entry)) {
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// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
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trigger(mandatory_request_type_to_event(in_msg.Type),
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in_msg.LineAddress, L1Icache_entry, tbe);
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} else {
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// Check to see if it is in the OTHER L1
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Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
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if (is_valid(L1Dcache_entry)) {
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// The block is in the wrong L1, try to write it to the L2
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if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
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trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
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} else {
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Address l2_victim_addr := L2cacheMemory.cacheProbe(in_msg.LineAddress);
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trigger(Event:L2_Replacement,
|
|
l2_victim_addr,
|
|
getL2CacheEntry(l2_victim_addr),
|
|
TBEs[l2_victim_addr]);
|
|
}
|
|
}
|
|
|
|
if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
|
|
// L1 does't have the line, but we have space for it in the L1
|
|
|
|
Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
|
|
if (is_valid(L2cache_entry)) {
|
|
// L2 has it (maybe not with the right permissions)
|
|
trigger(Event:Trigger_L2_to_L1I, in_msg.LineAddress,
|
|
L2cache_entry, tbe);
|
|
} else {
|
|
// We have room, the L2 doesn't have it, so the L1 fetches the line
|
|
trigger(mandatory_request_type_to_event(in_msg.Type),
|
|
in_msg.LineAddress, L1Icache_entry, tbe);
|
|
}
|
|
} else {
|
|
// No room in the L1, so we need to make room
|
|
Address l1i_victim_addr := L1IcacheMemory.cacheProbe(in_msg.LineAddress);
|
|
if (L2cacheMemory.cacheAvail(l1i_victim_addr)) {
|
|
// The L2 has room, so we move the line from the L1 to the L2
|
|
trigger(Event:L1_to_L2,
|
|
l1i_victim_addr,
|
|
getL1ICacheEntry(l1i_victim_addr),
|
|
TBEs[l1i_victim_addr]);
|
|
} else {
|
|
Address l2_victim_addr := L2cacheMemory.cacheProbe(l1i_victim_addr);
|
|
// The L2 does not have room, so we replace a line from the L2
|
|
trigger(Event:L2_Replacement,
|
|
l2_victim_addr,
|
|
getL2CacheEntry(l2_victim_addr),
|
|
TBEs[l2_victim_addr]);
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
// *** DATA ACCESS ***
|
|
|
|
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
|
|
if (is_valid(L1Dcache_entry)) {
|
|
// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
|
|
trigger(mandatory_request_type_to_event(in_msg.Type),
|
|
in_msg.LineAddress, L1Dcache_entry, tbe);
|
|
} else {
|
|
|
|
// Check to see if it is in the OTHER L1
|
|
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
|
|
if (is_valid(L1Icache_entry)) {
|
|
// The block is in the wrong L1, try to write it to the L2
|
|
if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
|
|
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
|
|
} else {
|
|
Address l2_victim_addr := L2cacheMemory.cacheProbe(in_msg.LineAddress);
|
|
trigger(Event:L2_Replacement,
|
|
l2_victim_addr,
|
|
getL2CacheEntry(l2_victim_addr),
|
|
TBEs[l2_victim_addr]);
|
|
}
|
|
}
|
|
|
|
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
|
|
// L1 does't have the line, but we have space for it in the L1
|
|
Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
|
|
if (is_valid(L2cache_entry)) {
|
|
// L2 has it (maybe not with the right permissions)
|
|
trigger(Event:Trigger_L2_to_L1D, in_msg.LineAddress,
|
|
L2cache_entry, tbe);
|
|
} else {
|
|
// We have room, the L2 doesn't have it, so the L1 fetches the line
|
|
trigger(mandatory_request_type_to_event(in_msg.Type),
|
|
in_msg.LineAddress, L1Dcache_entry, tbe);
|
|
}
|
|
} else {
|
|
// No room in the L1, so we need to make room
|
|
Address l1d_victim_addr := L1DcacheMemory.cacheProbe(in_msg.LineAddress);
|
|
if (L2cacheMemory.cacheAvail(l1d_victim_addr)) {
|
|
// The L2 has room, so we move the line from the L1 to the L2
|
|
trigger(Event:L1_to_L2,
|
|
l1d_victim_addr,
|
|
getL1DCacheEntry(l1d_victim_addr),
|
|
TBEs[l1d_victim_addr]);
|
|
} else {
|
|
Address l2_victim_addr := L2cacheMemory.cacheProbe(l1d_victim_addr);
|
|
// The L2 does not have room, so we replace a line from the L2
|
|
trigger(Event:L2_Replacement,
|
|
l2_victim_addr,
|
|
getL2CacheEntry(l2_victim_addr),
|
|
TBEs[l2_victim_addr]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// ACTIONS
|
|
|
|
action(a_issueGETS, "a", desc="Issue GETS") {
|
|
enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:GETS;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
out_msg.InitialRequestTime := get_time();
|
|
tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
|
|
}
|
|
}
|
|
|
|
action(b_issueGETX, "b", desc="Issue GETX") {
|
|
enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:GETX;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
out_msg.InitialRequestTime := get_time();
|
|
tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
|
|
}
|
|
}
|
|
|
|
action(b_issueGETXIfMoreThanOne, "bo", desc="Issue GETX") {
|
|
if (machineCount(MachineType:L1Cache) > 1) {
|
|
enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:GETX;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
out_msg.InitialRequestTime := get_time();
|
|
}
|
|
}
|
|
tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
|
|
}
|
|
|
|
action(bf_issueGETF, "bf", desc="Issue GETF") {
|
|
enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:GETF;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Request_Control;
|
|
out_msg.InitialRequestTime := get_time();
|
|
tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
|
|
}
|
|
}
|
|
|
|
action(c_sendExclusiveData, "c", desc="Send exclusive data from cache to requestor") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
if (in_msg.DirectedProbe) {
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
} else {
|
|
out_msg.Acks := 2;
|
|
}
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(ct_sendExclusiveDataFromTBE, "ct", desc="Send exclusive data from tbe to requestor") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
if (in_msg.DirectedProbe) {
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
} else {
|
|
out_msg.Acks := 2;
|
|
}
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(d_issuePUT, "d", desc="Issue PUT") {
|
|
enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:PUT;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
|
|
action(df_issuePUTF, "df", desc="Issue PUTF") {
|
|
enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceRequestType:PUTF;
|
|
out_msg.Requestor := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
|
|
action(e_sendData, "e", desc="Send data from cache to requestor") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
if (in_msg.DirectedProbe) {
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
} else {
|
|
out_msg.Acks := 2;
|
|
}
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(ee_sendDataShared, "\e", desc="Send data from cache to requestor, remaining the owner") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_SHARED;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
|
|
if (in_msg.DirectedProbe) {
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
} else {
|
|
out_msg.Acks := 2;
|
|
}
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(et_sendDataSharedFromTBE, "\et", desc="Send data from TBE to requestor, keep a shared copy") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_SHARED;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
|
|
if (in_msg.DirectedProbe) {
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
} else {
|
|
out_msg.Acks := 2;
|
|
}
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all requestors, still the owner") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_SHARED;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination := in_msg.MergedRequestors;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(emt_sendDataSharedMultipleFromTBE, "emt", desc="Send data from tbe to all requestors") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_SHARED;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination := in_msg.MergedRequestors;
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk);
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(f_sendAck, "f", desc="Send ack from cache to requestor") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:ACK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.Acks := 1;
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
assert(in_msg.DirectedProbe == false);
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(ff_sendAckShared, "\f", desc="Send shared ack from cache to requestor") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:ACK_SHARED;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.Acks := 1;
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
assert(in_msg.DirectedProbe == false);
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(g_sendUnblock, "g", desc="Send unblock to memory") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:UNBLOCK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
}
|
|
}
|
|
|
|
action(gm_sendUnblockM, "gm", desc="Send unblock to memory and indicate M/O/E state") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:UNBLOCKM;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
}
|
|
}
|
|
|
|
action(gs_sendUnblockS, "gs", desc="Send unblock to memory and indicate S state") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:UNBLOCKS;
|
|
out_msg.Sender := machineID;
|
|
out_msg.CurOwner := tbe.CurOwner;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
}
|
|
}
|
|
|
|
action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
sequencer.readCallback(address, testAndClearLocalHit(cache_entry),
|
|
cache_entry.DataBlk);
|
|
}
|
|
|
|
action(hx_external_load_hit, "hx", desc="load required external msgs") {
|
|
assert(is_valid(cache_entry));
|
|
assert(is_valid(tbe));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
|
|
sequencer.readCallback(address,
|
|
getNondirectHitMachType(in_msg.Address, in_msg.Sender),
|
|
cache_entry.DataBlk,
|
|
tbe.InitialRequestTime,
|
|
tbe.ForwardRequestTime,
|
|
tbe.FirstResponseTime);
|
|
}
|
|
}
|
|
|
|
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
sequencer.writeCallback(address, testAndClearLocalHit(cache_entry),
|
|
cache_entry.DataBlk);
|
|
|
|
cache_entry.Dirty := true;
|
|
if (in_msg.Type == RubyRequestType:ATOMIC) {
|
|
cache_entry.AtomicAccessed := true;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(hh_flush_hit, "\hf", desc="Notify sequencer that flush completed.") {
|
|
assert(is_valid(tbe));
|
|
DPRINTF(RubySlicc, "%s\n", tbe.DataBlk);
|
|
sequencer.writeCallback(address, GenericMachineType:L1Cache,tbe.DataBlk);
|
|
}
|
|
|
|
action(sx_external_store_hit, "sx", desc="store required external msgs.") {
|
|
assert(is_valid(cache_entry));
|
|
assert(is_valid(tbe));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
|
|
sequencer.writeCallback(address,
|
|
getNondirectHitMachType(address, in_msg.Sender),
|
|
cache_entry.DataBlk,
|
|
tbe.InitialRequestTime,
|
|
tbe.ForwardRequestTime,
|
|
tbe.FirstResponseTime);
|
|
}
|
|
cache_entry.Dirty := true;
|
|
}
|
|
|
|
action(sxt_trig_ext_store_hit, "sxt", desc="store required external msgs.") {
|
|
assert(is_valid(cache_entry));
|
|
assert(is_valid(tbe));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
|
|
sequencer.writeCallback(address,
|
|
getNondirectHitMachType(address, tbe.LastResponder),
|
|
cache_entry.DataBlk,
|
|
tbe.InitialRequestTime,
|
|
tbe.ForwardRequestTime,
|
|
tbe.FirstResponseTime);
|
|
|
|
cache_entry.Dirty := true;
|
|
}
|
|
|
|
action(i_allocateTBE, "i", desc="Allocate TBE") {
|
|
check_allocate(TBEs);
|
|
assert(is_valid(cache_entry));
|
|
TBEs.allocate(address);
|
|
set_tbe(TBEs[address]);
|
|
tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
|
|
tbe.Dirty := cache_entry.Dirty;
|
|
tbe.Sharers := false;
|
|
}
|
|
|
|
action(it_allocateTBE, "it", desc="Allocate TBE") {
|
|
check_allocate(TBEs);
|
|
TBEs.allocate(address);
|
|
set_tbe(TBEs[address]);
|
|
tbe.Dirty := false;
|
|
tbe.Sharers := false;
|
|
}
|
|
|
|
action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
|
|
triggerQueue_in.dequeue();
|
|
}
|
|
|
|
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
|
|
mandatoryQueue_in.dequeue();
|
|
}
|
|
|
|
action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
|
|
forwardToCache_in.dequeue();
|
|
}
|
|
|
|
action(hp_copyFromTBEToL2, "li", desc="Copy data from TBE to L2 cache entry.") {
|
|
assert(is_valid(cache_entry));
|
|
assert(is_valid(tbe));
|
|
cache_entry.Dirty := tbe.Dirty;
|
|
cache_entry.DataBlk := tbe.DataBlk;
|
|
}
|
|
|
|
action(nb_copyFromTBEToL1, "fu", desc="Copy data from TBE to L1 cache entry.") {
|
|
assert(is_valid(cache_entry));
|
|
assert(is_valid(tbe));
|
|
cache_entry.Dirty := tbe.Dirty;
|
|
cache_entry.DataBlk := tbe.DataBlk;
|
|
cache_entry.FromL2 := true;
|
|
}
|
|
|
|
action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
assert(in_msg.Acks >= 0);
|
|
assert(is_valid(tbe));
|
|
DPRINTF(RubySlicc, "Sender = %s\n", in_msg.Sender);
|
|
DPRINTF(RubySlicc, "SilentAcks = %d\n", in_msg.SilentAcks);
|
|
if (tbe.AppliedSilentAcks == false) {
|
|
tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.SilentAcks;
|
|
tbe.AppliedSilentAcks := true;
|
|
}
|
|
DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
|
|
tbe.NumPendingMsgs := tbe.NumPendingMsgs - in_msg.Acks;
|
|
DPRINTF(RubySlicc, "%d\n", tbe.NumPendingMsgs);
|
|
APPEND_TRANSITION_COMMENT(tbe.NumPendingMsgs);
|
|
APPEND_TRANSITION_COMMENT(in_msg.Sender);
|
|
tbe.LastResponder := in_msg.Sender;
|
|
if (tbe.InitialRequestTime != zero_time() && in_msg.InitialRequestTime != zero_time()) {
|
|
assert(tbe.InitialRequestTime == in_msg.InitialRequestTime);
|
|
}
|
|
if (in_msg.InitialRequestTime != zero_time()) {
|
|
tbe.InitialRequestTime := in_msg.InitialRequestTime;
|
|
}
|
|
if (tbe.ForwardRequestTime != zero_time() && in_msg.ForwardRequestTime != zero_time()) {
|
|
assert(tbe.ForwardRequestTime == in_msg.ForwardRequestTime);
|
|
}
|
|
if (in_msg.ForwardRequestTime != zero_time()) {
|
|
tbe.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
if (tbe.FirstResponseTime == zero_time()) {
|
|
tbe.FirstResponseTime := get_time();
|
|
}
|
|
}
|
|
}
|
|
action(uo_updateCurrentOwner, "uo", desc="When moving SS state, update current owner.") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
assert(is_valid(tbe));
|
|
tbe.CurOwner := in_msg.Sender;
|
|
}
|
|
}
|
|
|
|
action(n_popResponseQueue, "n", desc="Pop response queue") {
|
|
responseToCache_in.dequeue();
|
|
}
|
|
|
|
action(ll_L2toL1Transfer, "ll", desc="") {
|
|
enqueue(triggerQueue_out, TriggerMsg, latency=l2_cache_hit_latency) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := TriggerType:L2_to_L1;
|
|
}
|
|
}
|
|
|
|
action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
|
|
assert(is_valid(tbe));
|
|
if (tbe.NumPendingMsgs == 0) {
|
|
enqueue(triggerQueue_out, TriggerMsg) {
|
|
out_msg.Address := address;
|
|
if (tbe.Sharers) {
|
|
out_msg.Type := TriggerType:ALL_ACKS;
|
|
} else {
|
|
out_msg.Type := TriggerType:ALL_ACKS_NO_SHARERS;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
action(p_decrementNumberOfMessagesByOne, "p", desc="Decrement the number of messages for which we're waiting by one") {
|
|
assert(is_valid(tbe));
|
|
tbe.NumPendingMsgs := tbe.NumPendingMsgs - 1;
|
|
}
|
|
|
|
action(pp_incrementNumberOfMessagesByOne, "\p", desc="Increment the number of messages for which we're waiting by one") {
|
|
assert(is_valid(tbe));
|
|
tbe.NumPendingMsgs := tbe.NumPendingMsgs + 1;
|
|
}
|
|
|
|
action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
assert(in_msg.Requestor != machineID);
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
if (in_msg.DirectedProbe) {
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
} else {
|
|
out_msg.Acks := 2;
|
|
}
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(sq_sendSharedDataFromTBEToCache, "sq", desc="Send shared data from TBE to cache, still the owner") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
assert(in_msg.Requestor != machineID);
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_SHARED;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
if (in_msg.DirectedProbe) {
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
} else {
|
|
out_msg.Acks := 2;
|
|
}
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(qm_sendDataFromTBEToCache, "qm", desc="Send data from TBE to cache, multiple sharers, still the owner") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_SHARED;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination := in_msg.MergedRequestors;
|
|
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
out_msg.Acks := machineCount(MachineType:L1Cache);
|
|
out_msg.SilentAcks := in_msg.SilentAcks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
out_msg.InitialRequestTime := in_msg.InitialRequestTime;
|
|
out_msg.ForwardRequestTime := in_msg.ForwardRequestTime;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.Dirty := tbe.Dirty;
|
|
if (tbe.Dirty) {
|
|
out_msg.Type := CoherenceResponseType:WB_DIRTY;
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
} else {
|
|
out_msg.Type := CoherenceResponseType:WB_CLEAN;
|
|
// NOTE: in a real system this would not send data. We send
|
|
// data here only so we can check it at the memory
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(r_setSharerBit, "r", desc="We saw other sharers") {
|
|
assert(is_valid(tbe));
|
|
tbe.Sharers := true;
|
|
}
|
|
|
|
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
|
|
TBEs.deallocate(address);
|
|
unset_tbe();
|
|
}
|
|
|
|
action(t_sendExclusiveDataFromTBEToMemory, "t", desc="Send exclusive data from TBE to memory") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency=cache_response_latency) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Address := address;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.Dirty := tbe.Dirty;
|
|
if (tbe.Dirty) {
|
|
out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_DIRTY;
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
} else {
|
|
out_msg.Type := CoherenceResponseType:WB_EXCLUSIVE_CLEAN;
|
|
// NOTE: in a real system this would not send data. We send
|
|
// data here only so we can check it at the memory
|
|
out_msg.DataBlk := tbe.DataBlk;
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(u_writeDataToCache, "u", desc="Write data to cache") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
cache_entry.Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(uf_writeDataToCacheTBE, "uf", desc="Write data to TBE") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
assert(is_valid(tbe));
|
|
tbe.DataBlk := in_msg.DataBlk;
|
|
tbe.Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
|
|
cache_entry.DataBlk, in_msg.DataBlk);
|
|
assert(cache_entry.DataBlk == in_msg.DataBlk);
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
cache_entry.Dirty := in_msg.Dirty || cache_entry.Dirty;
|
|
}
|
|
}
|
|
|
|
action(vt_writeDataToTBEVerify, "vt", desc="Write data to TBE, assert it was same as before") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
assert(is_valid(tbe));
|
|
DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n",
|
|
tbe.DataBlk, in_msg.DataBlk);
|
|
assert(tbe.DataBlk == in_msg.DataBlk);
|
|
tbe.DataBlk := in_msg.DataBlk;
|
|
tbe.Dirty := in_msg.Dirty || tbe.Dirty;
|
|
}
|
|
}
|
|
|
|
action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
|
|
if (L1DcacheMemory.isTagPresent(address)) {
|
|
L1DcacheMemory.deallocate(address);
|
|
} else {
|
|
L1IcacheMemory.deallocate(address);
|
|
}
|
|
unset_cache_entry();
|
|
}
|
|
|
|
action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
|
|
set_cache_entry(L2cacheMemory.allocate(address, new Entry));
|
|
}
|
|
|
|
action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
|
|
L2cacheMemory.deallocate(address);
|
|
unset_cache_entry();
|
|
}
|
|
|
|
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
|
|
if (send_evictions) {
|
|
DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
|
|
sequencer.evictionCallback(address);
|
|
}
|
|
}
|
|
|
|
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
if (L1IcacheMemory.isTagPresent(address)) {
|
|
L1IcacheMemory.profileMiss(in_msg);
|
|
} else if (L1DcacheMemory.isTagPresent(address)) {
|
|
L1DcacheMemory.profileMiss(in_msg);
|
|
}
|
|
if (L2cacheMemory.isTagPresent(address) == false) {
|
|
L2cacheMemory.profileMiss(in_msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
|
|
stall_and_wait(mandatoryQueue_in, address);
|
|
}
|
|
|
|
action(z_stall, "z", desc="stall") {
|
|
// do nothing and the special z_stall action will return a protocol stall
|
|
// so that the next port is checked
|
|
}
|
|
|
|
action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
|
|
wakeUpBuffers(address);
|
|
}
|
|
|
|
action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
|
|
wakeUpAllBuffers();
|
|
}
|
|
|
|
//*****************************************************
|
|
// TRANSITIONS
|
|
//*****************************************************
|
|
|
|
// Transitions for Load/Store/L2_Replacement from transient states
|
|
transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) {
|
|
zz_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II}, {Flush_line}) {
|
|
zz_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({M_W, MM_W}, {L2_Replacement, Flush_line}) {
|
|
zz_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT, MI_F, MM_F, OM_F, IM_F, ISM_F, SM_F, MM_WF}, {Load, Ifetch}) {
|
|
zz_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT, IM_F, SM_F, ISM_F, OM_F, MM_WF, MI_F, MM_F, IR, SR, OR, MR, MMR}, L1_to_L2) {
|
|
zz_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({MI_F, MM_F}, {Store}) {
|
|
zz_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({MM_F, MI_F}, {Flush_line}) {
|
|
zz_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate, Flush_line}) {
|
|
z_stall;
|
|
}
|
|
|
|
transition({IR, SR, OR, MR, MMR}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
|
|
z_stall;
|
|
}
|
|
|
|
// Transitions moving data between the L1 and L2 caches
|
|
transition({I, S, O, M, MM}, L1_to_L2) {
|
|
i_allocateTBE;
|
|
gg_deallocateL1CacheBlock;
|
|
vv_allocateL2CacheBlock;
|
|
hp_copyFromTBEToL2;
|
|
s_deallocateTBE;
|
|
}
|
|
|
|
transition(I, Trigger_L2_to_L1D, IT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
ii_allocateL1DCacheBlock;
|
|
nb_copyFromTBEToL1; // Not really needed for state I
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(S, Trigger_L2_to_L1D, ST) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
ii_allocateL1DCacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(O, Trigger_L2_to_L1D, OT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
ii_allocateL1DCacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(M, Trigger_L2_to_L1D, MT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
ii_allocateL1DCacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(MM, Trigger_L2_to_L1D, MMT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
ii_allocateL1DCacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(I, Trigger_L2_to_L1I, IT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
jj_allocateL1ICacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(S, Trigger_L2_to_L1I, ST) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
jj_allocateL1ICacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(O, Trigger_L2_to_L1I, OT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
jj_allocateL1ICacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(M, Trigger_L2_to_L1I, MT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
jj_allocateL1ICacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(MM, Trigger_L2_to_L1I, MMT) {
|
|
i_allocateTBE;
|
|
rr_deallocateL2CacheBlock;
|
|
jj_allocateL1ICacheBlock;
|
|
nb_copyFromTBEToL1;
|
|
s_deallocateTBE;
|
|
uu_profileMiss;
|
|
zz_stallAndWaitMandatoryQueue;
|
|
ll_L2toL1Transfer;
|
|
}
|
|
|
|
transition(IT, Complete_L2_to_L1, IR) {
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(ST, Complete_L2_to_L1, SR) {
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(OT, Complete_L2_to_L1, OR) {
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(MT, Complete_L2_to_L1, MR) {
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(MMT, Complete_L2_to_L1, MMR) {
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
// Transitions from Idle
|
|
transition({I, IR}, Load, IS) {
|
|
ii_allocateL1DCacheBlock;
|
|
i_allocateTBE;
|
|
a_issueGETS;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({I, IR}, Ifetch, IS) {
|
|
jj_allocateL1ICacheBlock;
|
|
i_allocateTBE;
|
|
a_issueGETS;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({I, IR}, Store, IM) {
|
|
ii_allocateL1DCacheBlock;
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({I, IR}, Flush_line, IM_F) {
|
|
it_allocateTBE;
|
|
bf_issueGETF;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, L2_Replacement) {
|
|
rr_deallocateL2CacheBlock;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from Shared
|
|
transition({S, SM, ISM}, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(SR, {Load, Ifetch}, S) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition({S, SR}, Store, SM) {
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({S, SR}, Flush_line, SM_F) {
|
|
i_allocateTBE;
|
|
bf_issueGETF;
|
|
uu_profileMiss;
|
|
forward_eviction_to_cpu;
|
|
gg_deallocateL1CacheBlock;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(S, L2_Replacement, I) {
|
|
forward_eviction_to_cpu;
|
|
rr_deallocateL2CacheBlock;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(S, {Other_GETX, Invalidate}, I) {
|
|
f_sendAck;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(S, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
|
|
ff_sendAckShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from Owned
|
|
transition({O, OM, SS, MM_W, M_W}, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(OR, {Load, Ifetch}, O) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition({O, OR}, Store, OM) {
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
p_decrementNumberOfMessagesByOne;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
transition({O, OR}, Flush_line, OM_F) {
|
|
i_allocateTBE;
|
|
bf_issueGETF;
|
|
p_decrementNumberOfMessagesByOne;
|
|
uu_profileMiss;
|
|
forward_eviction_to_cpu;
|
|
gg_deallocateL1CacheBlock;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(O, L2_Replacement, OI) {
|
|
i_allocateTBE;
|
|
d_issuePUT;
|
|
forward_eviction_to_cpu;
|
|
rr_deallocateL2CacheBlock;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(O, {Other_GETX, Invalidate}, I) {
|
|
e_sendData;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(O, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
|
|
ee_sendDataShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(O, Merged_GETS) {
|
|
em_sendDataSharedMultiple;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from Modified
|
|
transition({MM, M}, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(MM, Store) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(MMR, {Load, Ifetch}, MM) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(MMR, Store, MM) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition({MM, M, MMR, MR}, Flush_line, MM_F) {
|
|
i_allocateTBE;
|
|
bf_issueGETF;
|
|
p_decrementNumberOfMessagesByOne;
|
|
forward_eviction_to_cpu;
|
|
gg_deallocateL1CacheBlock;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(MM_F, Block_Ack, MI_F) {
|
|
df_issuePUTF;
|
|
l_popForwardQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(MM, L2_Replacement, MI) {
|
|
i_allocateTBE;
|
|
d_issuePUT;
|
|
forward_eviction_to_cpu;
|
|
rr_deallocateL2CacheBlock;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(MM, {Other_GETX, Invalidate}, I) {
|
|
c_sendExclusiveData;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM, Other_GETS, I) {
|
|
c_sendExclusiveData;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM, NC_DMA_GETS, O) {
|
|
ee_sendDataShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM, Other_GETS_No_Mig, O) {
|
|
ee_sendDataShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM, Merged_GETS, O) {
|
|
em_sendDataSharedMultiple;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from Dirty Exclusive
|
|
transition(M, Store, MM) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(MR, {Load, Ifetch}, M) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(MR, Store, MM) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(M, L2_Replacement, MI) {
|
|
i_allocateTBE;
|
|
d_issuePUT;
|
|
forward_eviction_to_cpu;
|
|
rr_deallocateL2CacheBlock;
|
|
ka_wakeUpAllDependents;
|
|
}
|
|
|
|
transition(M, {Other_GETX, Invalidate}, I) {
|
|
c_sendExclusiveData;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(M, {Other_GETS, Other_GETS_No_Mig}, O) {
|
|
ee_sendDataShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(M, NC_DMA_GETS, O) {
|
|
ee_sendDataShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(M, Merged_GETS, O) {
|
|
em_sendDataSharedMultiple;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from IM
|
|
|
|
transition({IM, IM_F}, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition({IM, IM_F, MM_F}, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IM, Data, ISM) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IM_F, Data, ISM_F) {
|
|
uf_writeDataToCacheTBE;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IM, Exclusive_Data, MM_W) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
sx_external_store_hit;
|
|
n_popResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(IM_F, Exclusive_Data, MM_WF) {
|
|
uf_writeDataToCacheTBE;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
// Transitions from SM
|
|
transition({SM, SM_F}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
|
|
ff_sendAckShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(SM, {Other_GETX, Invalidate}, IM) {
|
|
f_sendAck;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(SM_F, {Other_GETX, Invalidate}, IM_F) {
|
|
f_sendAck;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition({SM, SM_F}, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(SM, {Data, Exclusive_Data}, ISM) {
|
|
v_writeDataToCacheVerify;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(SM_F, {Data, Exclusive_Data}, ISM_F) {
|
|
vt_writeDataToTBEVerify;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
// Transitions from ISM
|
|
transition({ISM, ISM_F}, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(ISM, All_acks_no_sharers, MM) {
|
|
sxt_trig_ext_store_hit;
|
|
gm_sendUnblockM;
|
|
s_deallocateTBE;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(ISM_F, All_acks_no_sharers, MI_F) {
|
|
df_issuePUTF;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
// Transitions from OM
|
|
|
|
transition(OM, {Other_GETX, Invalidate}, IM) {
|
|
e_sendData;
|
|
pp_incrementNumberOfMessagesByOne;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM_F, {Other_GETX, Invalidate}, IM_F) {
|
|
q_sendDataFromTBEToCache;
|
|
pp_incrementNumberOfMessagesByOne;
|
|
forward_eviction_to_cpu;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
|
|
ee_sendDataShared;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM, Merged_GETS) {
|
|
em_sendDataSharedMultiple;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM_F, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
|
|
et_sendDataSharedFromTBE;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM_F, Merged_GETS) {
|
|
emt_sendDataSharedMultipleFromTBE;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition({OM, OM_F}, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(OM, {All_acks, All_acks_no_sharers}, MM) {
|
|
sxt_trig_ext_store_hit;
|
|
gm_sendUnblockM;
|
|
s_deallocateTBE;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition({MM_F, OM_F}, {All_acks, All_acks_no_sharers}, MI_F) {
|
|
df_issuePUTF;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
// Transitions from IS
|
|
|
|
transition(IS, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(IS, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IS, Shared_Ack) {
|
|
m_decrementNumberOfMessages;
|
|
r_setSharerBit;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IS, Data, SS) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
hx_external_load_hit;
|
|
uo_updateCurrentOwner;
|
|
n_popResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(IS, Exclusive_Data, M_W) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
hx_external_load_hit;
|
|
n_popResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(IS, Shared_Data, SS) {
|
|
u_writeDataToCache;
|
|
r_setSharerBit;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
hx_external_load_hit;
|
|
uo_updateCurrentOwner;
|
|
n_popResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
// Transitions from SS
|
|
|
|
transition(SS, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(SS, Shared_Ack) {
|
|
m_decrementNumberOfMessages;
|
|
r_setSharerBit;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(SS, All_acks, S) {
|
|
gs_sendUnblockS;
|
|
s_deallocateTBE;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(SS, All_acks_no_sharers, S) {
|
|
// Note: The directory might still be the owner, so that is why we go to S
|
|
gs_sendUnblockS;
|
|
s_deallocateTBE;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
// Transitions from MM_W
|
|
|
|
transition(MM_W, Store) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({MM_W, MM_WF}, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(MM_W, All_acks_no_sharers, MM) {
|
|
gm_sendUnblockM;
|
|
s_deallocateTBE;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(MM_WF, All_acks_no_sharers, MI_F) {
|
|
df_issuePUTF;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
// Transitions from M_W
|
|
|
|
transition(M_W, Store, MM_W) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(M_W, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(M_W, All_acks_no_sharers, M) {
|
|
gm_sendUnblockM;
|
|
s_deallocateTBE;
|
|
j_popTriggerQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
// Transitions from OI/MI
|
|
|
|
transition({OI, MI}, {Other_GETX, Invalidate}, II) {
|
|
q_sendDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition({OI, MI}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}, OI) {
|
|
sq_sendSharedDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition({OI, MI}, Merged_GETS, OI) {
|
|
qm_sendDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MI, Writeback_Ack, I) {
|
|
t_sendExclusiveDataFromTBEToMemory;
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(MI_F, Writeback_Ack, I) {
|
|
hh_flush_hit;
|
|
t_sendExclusiveDataFromTBEToMemory;
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(OI, Writeback_Ack, I) {
|
|
qq_sendDataFromTBEToMemory;
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
// Transitions from II
|
|
transition(II, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Other_GETX, Invalidate}, II) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(II, Writeback_Ack, I) {
|
|
g_sendUnblock;
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(II, Writeback_Nack, I) {
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(MM_F, {Other_GETX, Invalidate}, IM_F) {
|
|
ct_sendExclusiveDataFromTBE;
|
|
pp_incrementNumberOfMessagesByOne;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM_F, Other_GETS, IM_F) {
|
|
ct_sendExclusiveDataFromTBE;
|
|
pp_incrementNumberOfMessagesByOne;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM_F, NC_DMA_GETS, OM_F) {
|
|
sq_sendSharedDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM_F, Other_GETS_No_Mig, OM_F) {
|
|
et_sendDataSharedFromTBE;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM_F, Merged_GETS, OM_F) {
|
|
emt_sendDataSharedMultipleFromTBE;
|
|
l_popForwardQueue;
|
|
}
|
|
}
|