Ali Saidi 4e8d2d1593 make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads ... src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42		2007-03-02 22:34:51 -05:00
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formats	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
base.isa	Implemented fbfss and fbpfcc instructions, and cleaned up branch code a little.	2007-01-30 16:12:38 -05:00
bitfields.isa	add pseduo instruction support for sparc	2007-02-21 21:06:17 -05:00
decoder.isa	make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads	2007-03-02 22:34:51 -05:00
includes.isa	add pseduo instruction support for sparc	2007-02-21 21:06:17 -05:00
main.isa	Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description.	2006-10-23 07:55:52 -04:00
operands.isa	make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads	2007-03-02 22:34:51 -05:00