1f6d5f8f84
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
95 lines
3.1 KiB
Python
95 lines
3.1 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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# Only build the communication if we have support for protobuf as the
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# tracing relies on it
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if env['HAVE_PROTOBUF']:
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SimObject('CommMonitor.py')
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Source('comm_monitor.cc')
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SimObject('AbstractMemory.py')
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SimObject('AddrMapper.py')
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SimObject('Bridge.py')
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SimObject('DRAMCtrl.py')
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SimObject('MemObject.py')
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SimObject('SimpleMemory.py')
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SimObject('XBar.py')
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Source('abstract_mem.cc')
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Source('addr_mapper.cc')
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Source('bridge.cc')
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Source('coherent_xbar.cc')
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Source('dram_ctrl.cc')
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Source('mem_object.cc')
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Source('mport.cc')
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Source('noncoherent_xbar.cc')
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Source('packet.cc')
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Source('port.cc')
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Source('packet_queue.cc')
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Source('port_proxy.cc')
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Source('physical.cc')
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Source('simple_mem.cc')
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Source('snoop_filter.cc')
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Source('tport.cc')
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Source('xbar.cc')
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if env['TARGET_ISA'] != 'null':
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Source('fs_translating_port_proxy.cc')
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Source('se_translating_port_proxy.cc')
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Source('page_table.cc')
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if env['TARGET_ISA'] == 'x86':
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Source('multi_level_page_table.cc')
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if env['HAVE_DRAMSIM']:
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SimObject('DRAMSim2.py')
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Source('dramsim2_wrapper.cc')
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Source('dramsim2.cc')
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DebugFlag('AddrRanges')
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DebugFlag('BaseXBar')
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DebugFlag('CoherentXBar')
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DebugFlag('NoncoherentXBar')
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DebugFlag('SnoopFilter')
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CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
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'SnoopFilter'])
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DebugFlag('Bridge')
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DebugFlag('CommMonitor')
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DebugFlag('DRAM')
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DebugFlag('DRAMPower')
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DebugFlag('DRAMState')
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DebugFlag('LLSC')
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DebugFlag('MMU')
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DebugFlag('MemoryAccess')
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DebugFlag('PacketQueue')
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DebugFlag("DRAMSim2")
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