19bb896bfe
A significant contributor to the need for adoptOrphanParams() is the practice of appending to SimObjectVectors which have already been assigned as children. This practice sidesteps the assignment operation for those appended SimObjects, which is where parent/child relationships are typically established. This patch reworks the config scripts that use append() on SimObjectVectors, which all happen to be in the x86 system configuration. At some point in the future, I hope to make SimObjectVectors immutable (by deriving from tuple rather than list), at which time this patch will be necessary for correct operation. For now, it just avoids some of the warning messages that get printed in adoptOrphanParams().
562 lines
22 KiB
Python
562 lines
22 KiB
Python
# Copyright (c) 2010 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Kevin Lim
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from m5.objects import *
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from Benchmarks import *
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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class MemBus(Bus):
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badaddr_responder = BadAddr()
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default = Self.badaddr_responder.pio
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def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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self = LinuxAlphaSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = MemBus(bus_id=1)
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.iobus)
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self.tsunami.ide.pio = self.iobus.port
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self.tsunami.ethernet.pio = self.iobus.port
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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return self
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def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self = LinuxAlphaSystem(physmem = physmem)
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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# Create pio bus to connect all device pio ports to rubymem's pio port
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self.piobus = Bus(bus_id=0)
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#
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# Pio functional accesses from devices need direct access to memory
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# RubyPort currently does support functional accesses. Therefore provide
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# the piobus a direct connection to physical memory
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#
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self.piobus.port = physmem.port
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.piobus)
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self.tsunami.ide.pio = self.piobus.port
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self.tsunami.ethernet.pio = self.piobus.port
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#
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# Store the dma devices for later connection to dma ruby ports.
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# Append an underscore to dma_devices to avoid the SimObjectVector check.
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#
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self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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return self
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def makeSparcSystem(mem_mode, mdesc = None):
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class CowMmDisk(MmDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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self = SparcSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = MemBus(bus_id=1)
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.t1000 = T1000()
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self.t1000.attachOnChipIO(self.membus)
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self.t1000.attachIO(self.iobus)
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self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
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self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.physmem2.port = self.membus.port
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self.rom.port = self.membus.port
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self.nvram.port = self.membus.port
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self.hypervisor_desc.port = self.membus.port
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self.partition_desc.port = self.membus.port
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self.intrctrl = IntrControl()
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self.disk0 = CowMmDisk()
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self.disk0.childImage(disk('disk.s10hw2'))
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self.disk0.pio = self.iobus.port
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self.reset_bin = binary('reset_new.bin')
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self.hypervisor_bin = binary('q_new.bin')
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self.openboot_bin = binary('openboot_new.bin')
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self.nvram_bin = binary('nvram1')
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self.hypervisor_desc_bin = binary('1up-hv.bin')
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self.partition_desc_bin = binary('1up-md.bin')
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return self
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def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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assert machine_type
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if bare_metal:
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self = ArmSystem()
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else:
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self = LinuxArmSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = MemBus(bus_id=1)
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self.membus.badaddr_responder.warn_access = "warn"
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.mem_mode = mem_mode
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if machine_type == "RealView_PBX":
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self.realview = RealViewPBX()
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elif machine_type == "RealView_EB":
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self.realview = RealViewEB()
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else:
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print "Unknown Machine Type"
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sys.exit(1)
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use_cf = False
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if mdesc.disk()[-4:] == ".img":
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use_cf = True
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self.cf0 = CowIdeDisk(driveID='master')
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self.cf0.childImage(mdesc.disk())
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self.realview.cf_ctrl.disks = [self.cf0]
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if bare_metal:
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# EOT character on UART will end the simulation
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self.realview.uart.end_on_eot = True
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self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
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zero = True)
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else:
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self.kernel = binary('vmlinux.arm')
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self.machine_type = machine_type
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boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
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'rw loglevel=8 '
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if use_cf:
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self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
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zero = True)
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boot_flags += "mem=256MB root=/dev/sda1 "
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self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
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size = '64MB'), zero = True)
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self.nvmem.port = self.membus.port
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self.boot_loader = binary('boot.arm')
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self.boot_loader_mem = self.nvmem
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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else:
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self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')),
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zero = True)
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self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'),
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size = '128MB'),
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file = disk(mdesc.disk()))
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self.diskmem.port = self.membus.port
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boot_flags += "mem=128MB slram=slram0,0x8000000,+0x8000000 " + \
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"mtdparts=slram0:- root=/dev/mtdblock0 "
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if mdesc.disk().count('android'):
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boot_flags += "init=/init "
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self.boot_osflags = boot_flags
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self.physmem.port = self.membus.port
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self.realview.attachOnChipIO(self.membus)
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self.realview.attachIO(self.iobus)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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return self
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def makeLinuxMipsSystem(mem_mode, mdesc = None):
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class BaseMalta(Malta):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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self = LinuxMipsSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = MemBus(bus_id=1)
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.physmem = PhysicalMemory(range = AddrRange('1GB'))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.malta = BaseMalta()
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self.malta.attachIO(self.iobus)
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self.malta.ide.pio = self.iobus.port
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self.malta.ethernet.pio = self.iobus.port
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.kernel = binary('mips/vmlinux')
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self.console = binary('mips/console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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return self
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def x86IOAddress(port):
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IO_address_space_base = 0x8000000000000000
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return IO_address_space_base + port
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def connectX86ClassicSystem(x86_sys):
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x86_sys.membus = MemBus(bus_id=1)
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x86_sys.physmem.port = x86_sys.membus.port
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# North Bridge
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x86_sys.iobus = Bus(bus_id=0)
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x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
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x86_sys.bridge.side_a = x86_sys.iobus.port
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x86_sys.bridge.side_b = x86_sys.membus.port
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# connect the io bus
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x86_sys.pc.attachIO(x86_sys.iobus)
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def connectX86RubySystem(x86_sys):
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# North Bridge
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x86_sys.piobus = Bus(bus_id=0)
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#
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# Pio functional accesses from devices need direct access to memory
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# RubyPort currently does support functional accesses. Therefore provide
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# the piobus a direct connection to physical memory
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#
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x86_sys.piobus.port = x86_sys.physmem.port
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x86_sys.pc.attachIO(x86_sys.piobus)
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def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
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if self == None:
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self = X86System()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.mem_mode = mem_mode
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# Physical memory
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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# Platform
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self.pc = Pc()
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# Create and connect the busses required by each memory system
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if Ruby:
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connectX86RubySystem(self)
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# add the ide to the list of dma devices that later need to attach to
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# dma controllers
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self._dma_devices = [self.pc.south_bridge.ide]
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else:
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connectX86ClassicSystem(self)
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self.intrctrl = IntrControl()
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# Disks
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disk0 = CowIdeDisk(driveID='master')
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disk2 = CowIdeDisk(driveID='master')
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disk0.childImage(mdesc.disk())
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disk2.childImage(disk('linux-bigswap2.img'))
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self.pc.south_bridge.ide.disks = [disk0, disk2]
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# Add in a Bios information structure.
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structures = [X86SMBiosBiosInformation()]
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self.smbios_table.structures = structures
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# Set up the Intel MP table
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base_entries = []
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ext_entries = []
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for i in xrange(numCPUs):
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bp = X86IntelMPProcessor(
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local_apic_id = i,
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local_apic_version = 0x14,
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enable = True,
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bootstrap = (i == 0))
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base_entries.append(bp)
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io_apic = X86IntelMPIOAPIC(
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id = numCPUs,
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version = 0x11,
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enable = True,
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address = 0xfec00000)
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self.pc.south_bridge.io_apic.apic_id = io_apic.id
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base_entries.append(io_apic)
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isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
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base_entries.append(isa_bus)
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pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
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base_entries.append(pci_bus)
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connect_busses = X86IntelMPBusHierarchy(bus_id=0,
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subtractive_decode=True, parent_bus=1)
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ext_entries.append(connect_busses)
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pci_dev4_inta = X86IntelMPIOIntAssignment(
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interrupt_type = 'INT',
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polarity = 'ConformPolarity',
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trigger = 'ConformTrigger',
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source_bus_id = 1,
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source_bus_irq = 0 + (4 << 2),
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dest_io_apic_id = io_apic.id,
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dest_io_apic_intin = 16)
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base_entries.append(pci_dev4_inta)
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def assignISAInt(irq, apicPin):
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assign_8259_to_apic = X86IntelMPIOIntAssignment(
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interrupt_type = 'ExtInt',
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polarity = 'ConformPolarity',
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trigger = 'ConformTrigger',
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source_bus_id = 0,
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source_bus_irq = irq,
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dest_io_apic_id = io_apic.id,
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dest_io_apic_intin = 0)
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base_entries.append(assign_8259_to_apic)
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assign_to_apic = X86IntelMPIOIntAssignment(
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interrupt_type = 'INT',
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polarity = 'ConformPolarity',
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trigger = 'ConformTrigger',
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source_bus_id = 0,
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source_bus_irq = irq,
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dest_io_apic_id = io_apic.id,
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dest_io_apic_intin = apicPin)
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base_entries.append(assign_to_apic)
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assignISAInt(0, 2)
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assignISAInt(1, 1)
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for i in range(3, 15):
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assignISAInt(i, i)
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self.intel_mp_table.base_entries = base_entries
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self.intel_mp_table.ext_entries = ext_entries
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def setWorkCountOptions(system, options):
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if options.work_item_id != None:
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system.work_item_id = options.work_item_id
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if options.work_begin_cpu_id_exit != None:
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system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
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if options.work_end_exit_count != None:
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system.work_end_exit_count = options.work_end_exit_count
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if options.work_end_checkpoint_count != None:
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system.work_end_ckpt_count = options.work_end_checkpoint_count
|
|
if options.work_begin_exit_count != None:
|
|
system.work_begin_exit_count = options.work_begin_exit_count
|
|
if options.work_begin_checkpoint_count != None:
|
|
system.work_begin_ckpt_count = options.work_begin_checkpoint_count
|
|
if options.work_cpus_checkpoint_count != None:
|
|
system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
|
|
|
|
|
|
def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
|
|
self = LinuxX86System()
|
|
|
|
# Build up the x86 system and then specialize it for Linux
|
|
makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
|
|
|
|
# We assume below that there's at least 1MB of memory. We'll require 2
|
|
# just to avoid corner cases.
|
|
assert(self.physmem.range.second.getValue() >= 0x200000)
|
|
|
|
self.e820_table.entries = \
|
|
[
|
|
# Mark the first megabyte of memory as reserved
|
|
X86E820Entry(addr = 0, size = '1MB', range_type = 2),
|
|
# Mark the rest as available
|
|
X86E820Entry(addr = 0x100000,
|
|
size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
|
|
range_type = 1)
|
|
]
|
|
|
|
# Command line
|
|
self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
|
|
'root=/dev/hda1'
|
|
return self
|
|
|
|
|
|
def makeDualRoot(testSystem, driveSystem, dumpfile):
|
|
self = Root()
|
|
self.testsys = testSystem
|
|
self.drivesys = driveSystem
|
|
self.etherlink = EtherLink()
|
|
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
|
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
|
|
|
|
if dumpfile:
|
|
self.etherdump = EtherDump(file=dumpfile)
|
|
self.etherlink.dump = Parent.etherdump
|
|
|
|
return self
|
|
|
|
def setMipsOptions(TestCPUClass):
|
|
#CP0 Configuration
|
|
TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
|
|
TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
|
|
TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
|
|
TestCPUClass.CoreParams.CP0_PRId_Revision = 0
|
|
|
|
#CP0 Interrupt Control
|
|
TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
|
|
TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
|
|
|
|
# Config Register
|
|
#TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
|
|
#TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
|
|
TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
|
|
TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
|
|
TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
|
|
TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
|
|
#TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
|
|
|
|
#Config 1 Register
|
|
TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
|
|
TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
|
|
# ***VERY IMPORTANT***
|
|
# Remember to modify CP0_Config1 according to cache specs
|
|
# Examine file ../common/Cache.py
|
|
TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
|
|
TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
|
|
TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
|
|
TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
|
|
TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
|
|
TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
|
|
TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
|
|
TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
|
|
TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
|
|
TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
|
|
TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
|
|
TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
|
|
TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
|
|
|
|
#Config 2 Register
|
|
TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
|
|
TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
|
|
TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
|
|
TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
|
|
TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
|
|
TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
|
|
TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
|
|
TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
|
|
TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
|
|
|
|
|
|
#Config 3 Register
|
|
TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
|
|
TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
|
|
TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
|
|
TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
|
|
TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
|
|
TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
|
|
TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
|
|
TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
|
|
TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
|
|
|
|
#SRS Ctl - HSS
|
|
TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
|
|
|
|
|
|
#TestCPUClass.CoreParams.tlb = TLB()
|
|
#TestCPUClass.CoreParams.UnifiedTLB = 1
|