003c08fa90
This patch makes the internal links within the network topology unidirectional, thus allowing any deadlock-free routing algorithms to be specified from the topology itself using weights. This patch also renames Mesh.py and MeshDirCorners.py to Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing). It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.
164 lines
7.2 KiB
Python
164 lines
7.2 KiB
Python
# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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from m5.params import *
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from m5.objects import *
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from BaseTopology import SimpleTopology
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# Creates a Mesh topology with 4 directories, one at each corner.
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# One L1 (and L2, depending on the protocol) are connected to each router.
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# XY routing is enforced (using link weights) to guarantee deadlock freedom.
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class MeshDirCorners_XY(SimpleTopology):
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description='MeshDirCorners_XY'
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def __init__(self, controllers):
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self.nodes = controllers
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def makeTopology(self, options, network, IntLink, ExtLink, Router):
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nodes = self.nodes
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num_routers = options.num_cpus
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num_rows = options.mesh_rows
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# First determine which nodes are cache cntrls vs. dirs vs. dma
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cache_nodes = []
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dir_nodes = []
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dma_nodes = []
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for node in nodes:
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if node.type == 'L1Cache_Controller' or \
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node.type == 'L2Cache_Controller':
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cache_nodes.append(node)
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elif node.type == 'Directory_Controller':
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dir_nodes.append(node)
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elif node.type == 'DMA_Controller':
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dma_nodes.append(node)
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# Obviously the number or rows must be <= the number of routers
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# and evenly divisible. Also the number of caches must be a
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# multiple of the number of routers and the number of directories
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# must be four.
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assert(num_rows <= num_routers)
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num_columns = int(num_routers / num_rows)
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assert(num_columns * num_rows == num_routers)
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caches_per_router, remainder = divmod(len(cache_nodes), num_routers)
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assert(remainder == 0)
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assert(len(dir_nodes) == 4)
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# Create the routers in the mesh
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routers = [Router(router_id=i) for i in range(num_routers)]
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network.routers = routers
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# link counter to set unique link ids
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link_count = 0
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# Connect each cache controller to the appropriate router
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ext_links = []
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for (i, n) in enumerate(cache_nodes):
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cntrl_level, router_id = divmod(i, num_routers)
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assert(cntrl_level < caches_per_router)
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ext_links.append(ExtLink(link_id=link_count, ext_node=n,
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int_node=routers[router_id]))
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link_count += 1
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# Connect the dir nodes to the corners.
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ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0],
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int_node=routers[0]))
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link_count += 1
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ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1],
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int_node=routers[num_columns - 1]))
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link_count += 1
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ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2],
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int_node=routers[num_routers - num_columns]))
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link_count += 1
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ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3],
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int_node=routers[num_routers - 1]))
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link_count += 1
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# Connect the dma nodes to router 0. These should only be DMA nodes.
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for (i, node) in enumerate(dma_nodes):
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assert(node.type == 'DMA_Controller')
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ext_links.append(ExtLink(link_id=link_count, ext_node=node,
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int_node=routers[0]))
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network.ext_links = ext_links
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# Create the mesh links.
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int_links = []
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# East output to West input links (weight = 1)
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for row in xrange(num_rows):
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for col in xrange(num_columns):
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if (col + 1 < num_columns):
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east_out = col + (row * num_columns)
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west_in = (col + 1) + (row * num_columns)
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int_links.append(IntLink(link_id=link_count,
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src_node=routers[east_out],
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dst_node=routers[west_in],
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weight=1))
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link_count += 1
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# West output to East input links (weight = 1)
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for row in xrange(num_rows):
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for col in xrange(num_columns):
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if (col + 1 < num_columns):
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east_in = col + (row * num_columns)
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west_out = (col + 1) + (row * num_columns)
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int_links.append(IntLink(link_id=link_count,
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src_node=routers[west_out],
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dst_node=routers[east_in],
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weight=1))
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link_count += 1
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# North output to South input links (weight = 2)
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for col in xrange(num_columns):
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for row in xrange(num_rows):
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if (row + 1 < num_rows):
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north_out = col + (row * num_columns)
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south_in = col + ((row + 1) * num_columns)
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int_links.append(IntLink(link_id=link_count,
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src_node=routers[north_out],
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dst_node=routers[south_in],
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weight=2))
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link_count += 1
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# South output to North input links (weight = 2)
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for col in xrange(num_columns):
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for row in xrange(num_rows):
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if (row + 1 < num_rows):
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north_in = col + (row * num_columns)
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south_out = col + ((row + 1) * num_columns)
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int_links.append(IntLink(link_id=link_count,
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src_node=routers[south_out],
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dst_node=routers[north_in],
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weight=2))
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link_count += 1
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network.int_links = int_links
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