1469 lines
38 KiB
Plaintext
1469 lines
38 KiB
Plaintext
|
|
================ Begin RubySystem Configuration Print ================
|
|
|
|
RubySystem config:
|
|
random_seed: 1234
|
|
randomization: 1
|
|
cycle_period: 1
|
|
block_size_bytes: 64
|
|
block_size_bits: 6
|
|
memory_size_bytes: 134217728
|
|
memory_size_bits: 27
|
|
|
|
Network Configuration
|
|
---------------------
|
|
network: SIMPLE_NETWORK
|
|
topology:
|
|
|
|
virtual_net_0: active, unordered
|
|
virtual_net_1: active, unordered
|
|
virtual_net_2: active, unordered
|
|
virtual_net_3: inactive
|
|
virtual_net_4: inactive
|
|
virtual_net_5: inactive
|
|
virtual_net_6: inactive
|
|
virtual_net_7: inactive
|
|
virtual_net_8: inactive
|
|
virtual_net_9: inactive
|
|
|
|
|
|
Profiler Configuration
|
|
----------------------
|
|
periodic_stats_period: 1000000
|
|
|
|
================ End RubySystem Configuration Print ================
|
|
|
|
|
|
Real time: Apr/28/2011 14:49:15
|
|
|
|
Profiler Stats
|
|
--------------
|
|
Elapsed_time_in_seconds: 0
|
|
Elapsed_time_in_minutes: 0
|
|
Elapsed_time_in_hours: 0
|
|
Elapsed_time_in_days: 0
|
|
|
|
Virtual_time_in_seconds: 1.04
|
|
Virtual_time_in_minutes: 0.0173333
|
|
Virtual_time_in_hours: 0.000288889
|
|
Virtual_time_in_days: 1.2037e-05
|
|
|
|
Ruby_current_time: 371241
|
|
Ruby_start_time: 0
|
|
Ruby_cycles: 371241
|
|
|
|
mbytes_resident: 36.1758
|
|
mbytes_total: 219.98
|
|
resident_ratio: 0.164503
|
|
|
|
ruby_cycles_executed: [ 371242 ]
|
|
|
|
Busy Controller Counts:
|
|
L2Cache-0:0
|
|
L1Cache-0:0
|
|
|
|
Directory-0:0
|
|
|
|
Busy Bank Count:0
|
|
|
|
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 993 average: 15.8197 | standard deviation: 1.13014 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 60 919 ]
|
|
|
|
All Non-Zero Cycle Demand Cache Accesses
|
|
----------------------------------------
|
|
miss_latency: [binsize: 256 max: 41885 count: 980 average: 5911.29 | standard deviation: 9158.49 | 92 27 107 116 84 56 57 54 23 16 22 11 13 12 11 6 8 7 8 3 3 6 5 4 5 3 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 1 4 4 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 6 1 6 2 4 3 2 1 1 2 2 3 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_LD: [binsize: 256 max: 28410 count: 50 average: 3572.56 | standard deviation: 6675.9 | 5 1 7 5 3 6 7 5 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_ST: [binsize: 256 max: 41885 count: 880 average: 6339.85 | standard deviation: 9428.49 | 84 21 77 99 75 49 50 49 23 15 21 11 13 12 11 5 7 7 8 3 3 6 5 4 4 2 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 0 4 3 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 5 1 6 2 4 3 2 1 1 2 1 2 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_IFETCH: [binsize: 8 max: 1453 count: 50 average: 707.26 | standard deviation: 269.766 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 2 1 1 0 0 0 1 0 1 0 1 0 4 2 1 0 1 0 1 0 1 1 0 0 0 0 2 0 1 2 0 0 0 0 0 0 0 0 2 1 0 1 1 0 1 0 0 3 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
|
miss_latency_NULL: [binsize: 256 max: 41885 count: 980 average: 5911.29 | standard deviation: 9158.49 | 92 27 107 116 84 56 57 54 23 16 22 11 13 12 11 6 8 7 8 3 3 6 5 4 5 3 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 1 4 4 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 6 1 6 2 4 3 2 1 1 2 2 3 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
imcomplete_wCC_Times: 0
|
|
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
imcomplete_dir_Times: 0
|
|
miss_latency_LD_NULL: [binsize: 256 max: 28410 count: 50 average: 3572.56 | standard deviation: 6675.9 | 5 1 7 5 3 6 7 5 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_ST_NULL: [binsize: 256 max: 41885 count: 880 average: 6339.85 | standard deviation: 9428.49 | 84 21 77 99 75 49 50 49 23 15 21 11 13 12 11 5 7 7 8 3 3 6 5 4 4 2 4 1 3 4 3 2 4 3 0 3 0 1 4 2 2 2 2 1 1 1 0 1 0 0 0 1 2 1 0 4 3 1 1 3 1 1 2 1 0 3 4 1 2 0 1 2 4 3 2 4 3 2 4 2 2 5 3 1 2 4 2 3 3 1 0 3 2 6 1 2 3 1 4 5 1 6 2 4 3 2 1 1 2 1 2 0 1 1 0 1 0 1 1 1 2 0 1 1 0 3 0 1 0 0 2 1 2 0 1 0 2 2 0 0 0 0 0 0 1 1 1 0 1 2 0 1 3 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
miss_latency_IFETCH_NULL: [binsize: 8 max: 1453 count: 50 average: 707.26 | standard deviation: 269.766 | 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 0 0 2 1 1 0 0 0 1 0 1 0 1 0 4 2 1 0 1 0 1 0 1 1 0 0 0 0 2 0 1 2 0 0 0 0 0 0 0 0 2 1 0 1 1 0 1 0 0 3 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
|
|
|
All Non-Zero Cycle SW Prefetch Requests
|
|
------------------------------------
|
|
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
Request vs. RubySystem State Profile
|
|
--------------------------------
|
|
|
|
|
|
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Message Delayed Cycles
|
|
----------------------
|
|
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
Resource Usage
|
|
--------------
|
|
page_size: 4096
|
|
user_time: 0
|
|
system_time: 0
|
|
page_reclaims: 10488
|
|
page_faults: 0
|
|
swaps: 0
|
|
block_inputs: 0
|
|
block_outputs: 0
|
|
|
|
Network Stats
|
|
-------------
|
|
|
|
total_msg_count_Request_Control: 5209 41672
|
|
total_msg_count_Response_Data: 5058 364176
|
|
total_msg_count_ResponseL2hit_Data: 150 10800
|
|
total_msg_count_Writeback_Data: 4929 354888
|
|
total_msg_count_Writeback_Control: 10567 84536
|
|
total_msg_count_Unblock_Control: 5193 41544
|
|
total_msgs: 31106 total_bytes: 897616
|
|
|
|
switch_0_inlinks: 2
|
|
switch_0_outlinks: 2
|
|
links_utilized_percent_switch_0: 2.51865
|
|
links_utilized_percent_switch_0_link_0: 2.57016 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_0_link_1: 2.46713 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_0_link_0_Request_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Writeback_Control: 1721 13768 [ 888 833 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_0_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Writeback_Control: 1802 14416 [ 888 836 78 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_0_link_1_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_1_inlinks: 2
|
|
switch_1_outlinks: 2
|
|
links_utilized_percent_switch_1: 1.31922
|
|
links_utilized_percent_switch_1_link_0: 1.20205 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_1_link_1: 1.4364 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_1_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_0_Writeback_Control: 888 7104 [ 888 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Request_Control: 894 7152 [ 894 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Writeback_Control: 889 7112 [ 889 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_1_link_1_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_2_inlinks: 2
|
|
switch_2_outlinks: 2
|
|
links_utilized_percent_switch_2: 1.19949
|
|
links_utilized_percent_switch_2_link_0: 1.26481 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_2_link_1: 1.13417 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_2_link_0_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Writeback_Control: 912 7296 [ 0 834 78 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_0_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_2_link_1_Writeback_Control: 834 6672 [ 0 834 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
switch_3_inlinks: 3
|
|
switch_3_outlinks: 3
|
|
links_utilized_percent_switch_3: 1.67901
|
|
links_utilized_percent_switch_3_link_0: 2.57016 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_3_link_1: 1.20205 bw: 16000 base_latency: 1
|
|
links_utilized_percent_switch_3_link_2: 1.26481 bw: 16000 base_latency: 1
|
|
|
|
outgoing_messages_switch_3_link_0_Request_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Writeback_Data: 888 63936 [ 0 0 888 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Writeback_Control: 1721 13768 [ 888 833 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_0_Unblock_Control: 890 7120 [ 0 0 890 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Response_Data: 843 60696 [ 0 0 843 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 50 3600 [ 0 0 50 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_1_Writeback_Control: 888 7104 [ 888 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_2_Request_Control: 843 6744 [ 0 843 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_2_Writeback_Data: 755 54360 [ 0 0 755 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_2_Writeback_Control: 912 7296 [ 0 834 78 0 0 0 0 0 0 0 ] base_latency: 1
|
|
outgoing_messages_switch_3_link_2_Unblock_Control: 841 6728 [ 0 0 841 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
|
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|
system.l1_cntrl0.L1DcacheMemory_total_misses: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
--- L1Cache ---
|
|
- Event Counts -
|
|
Load [50 ] 50
|
|
Ifetch [304 ] 304
|
|
Store [970 ] 970
|
|
L1_Replacement [527165 ] 527165
|
|
Own_GETX [0 ] 0
|
|
Fwd_GETX [0 ] 0
|
|
Fwd_GETS [0 ] 0
|
|
Fwd_DMA [0 ] 0
|
|
Inv [0 ] 0
|
|
Ack [0 ] 0
|
|
Data [0 ] 0
|
|
Exclusive_Data [893 ] 893
|
|
Writeback_Ack [0 ] 0
|
|
Writeback_Ack_Data [888 ] 888
|
|
Writeback_Nack [0 ] 0
|
|
All_acks [799 ] 799
|
|
Use_Timeout [890 ] 890
|
|
|
|
- Transitions -
|
|
I Load [45 ] 45
|
|
I Ifetch [49 ] 49
|
|
I Store [800 ] 800
|
|
I L1_Replacement [0 ] 0
|
|
I Inv [0 ] 0
|
|
|
|
S Load [0 ] 0
|
|
S Ifetch [0 ] 0
|
|
S Store [0 ] 0
|
|
S L1_Replacement [0 ] 0
|
|
S Fwd_GETS [0 ] 0
|
|
S Fwd_DMA [0 ] 0
|
|
S Inv [0 ] 0
|
|
|
|
O Load [0 ] 0
|
|
O Ifetch [0 ] 0
|
|
O Store [0 ] 0
|
|
O L1_Replacement [0 ] 0
|
|
O Fwd_GETX [0 ] 0
|
|
O Fwd_GETS [0 ] 0
|
|
O Fwd_DMA [0 ] 0
|
|
|
|
M Load [0 ] 0
|
|
M Ifetch [1 ] 1
|
|
M Store [0 ] 0
|
|
M L1_Replacement [91 ] 91
|
|
M Fwd_GETX [0 ] 0
|
|
M Fwd_GETS [0 ] 0
|
|
M Fwd_DMA [0 ] 0
|
|
|
|
M_W Load [0 ] 0
|
|
M_W Ifetch [0 ] 0
|
|
M_W Store [0 ] 0
|
|
M_W L1_Replacement [1727 ] 1727
|
|
M_W Own_GETX [0 ] 0
|
|
M_W Fwd_GETX [0 ] 0
|
|
M_W Fwd_GETS [0 ] 0
|
|
M_W Fwd_DMA [0 ] 0
|
|
M_W Inv [0 ] 0
|
|
M_W Use_Timeout [92 ] 92
|
|
|
|
MM Load [5 ] 5
|
|
MM Ifetch [0 ] 0
|
|
MM Store [70 ] 70
|
|
MM L1_Replacement [798 ] 798
|
|
MM Fwd_GETX [0 ] 0
|
|
MM Fwd_GETS [0 ] 0
|
|
MM Fwd_DMA [0 ] 0
|
|
|
|
MM_W Load [0 ] 0
|
|
MM_W Ifetch [0 ] 0
|
|
MM_W Store [11 ] 11
|
|
MM_W L1_Replacement [29093 ] 29093
|
|
MM_W Own_GETX [0 ] 0
|
|
MM_W Fwd_GETX [0 ] 0
|
|
MM_W Fwd_GETS [0 ] 0
|
|
MM_W Fwd_DMA [0 ] 0
|
|
MM_W Inv [0 ] 0
|
|
MM_W Use_Timeout [798 ] 798
|
|
|
|
IM Load [0 ] 0
|
|
IM Ifetch [0 ] 0
|
|
IM Store [0 ] 0
|
|
IM L1_Replacement [453807 ] 453807
|
|
IM Inv [0 ] 0
|
|
IM Ack [0 ] 0
|
|
IM Data [0 ] 0
|
|
IM Exclusive_Data [799 ] 799
|
|
|
|
SM Load [0 ] 0
|
|
SM Ifetch [0 ] 0
|
|
SM Store [0 ] 0
|
|
SM L1_Replacement [0 ] 0
|
|
SM Fwd_GETS [0 ] 0
|
|
SM Fwd_DMA [0 ] 0
|
|
SM Inv [0 ] 0
|
|
SM Ack [0 ] 0
|
|
SM Data [0 ] 0
|
|
SM Exclusive_Data [0 ] 0
|
|
|
|
OM Load [0 ] 0
|
|
OM Ifetch [0 ] 0
|
|
OM Store [0 ] 0
|
|
OM L1_Replacement [14583 ] 14583
|
|
OM Own_GETX [0 ] 0
|
|
OM Fwd_GETX [0 ] 0
|
|
OM Fwd_GETS [0 ] 0
|
|
OM Fwd_DMA [0 ] 0
|
|
OM Ack [0 ] 0
|
|
OM All_acks [799 ] 799
|
|
|
|
IS Load [0 ] 0
|
|
IS Ifetch [0 ] 0
|
|
IS Store [0 ] 0
|
|
IS L1_Replacement [27066 ] 27066
|
|
IS Inv [0 ] 0
|
|
IS Data [0 ] 0
|
|
IS Exclusive_Data [94 ] 94
|
|
|
|
SI Load [0 ] 0
|
|
SI Ifetch [0 ] 0
|
|
SI Store [0 ] 0
|
|
SI L1_Replacement [0 ] 0
|
|
SI Fwd_GETS [0 ] 0
|
|
SI Fwd_DMA [0 ] 0
|
|
SI Inv [0 ] 0
|
|
SI Writeback_Ack [0 ] 0
|
|
SI Writeback_Ack_Data [0 ] 0
|
|
SI Writeback_Nack [0 ] 0
|
|
|
|
OI Load [0 ] 0
|
|
OI Ifetch [0 ] 0
|
|
OI Store [0 ] 0
|
|
OI L1_Replacement [0 ] 0
|
|
OI Fwd_GETX [0 ] 0
|
|
OI Fwd_GETS [0 ] 0
|
|
OI Fwd_DMA [0 ] 0
|
|
OI Writeback_Ack [0 ] 0
|
|
OI Writeback_Ack_Data [0 ] 0
|
|
OI Writeback_Nack [0 ] 0
|
|
|
|
MI Load [0 ] 0
|
|
MI Ifetch [254 ] 254
|
|
MI Store [89 ] 89
|
|
MI L1_Replacement [0 ] 0
|
|
MI Fwd_GETX [0 ] 0
|
|
MI Fwd_GETS [0 ] 0
|
|
MI Fwd_DMA [0 ] 0
|
|
MI Writeback_Ack [0 ] 0
|
|
MI Writeback_Ack_Data [888 ] 888
|
|
MI Writeback_Nack [0 ] 0
|
|
|
|
II Load [0 ] 0
|
|
II Ifetch [0 ] 0
|
|
II Store [0 ] 0
|
|
II L1_Replacement [0 ] 0
|
|
II Inv [0 ] 0
|
|
II Writeback_Ack [0 ] 0
|
|
II Writeback_Ack_Data [0 ] 0
|
|
II Writeback_Nack [0 ] 0
|
|
|
|
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|
system.l2_cntrl0.L2cacheMemory_total_misses: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
--- L2Cache ---
|
|
- Event Counts -
|
|
L1_GETS [157 ] 157
|
|
L1_GETX [842 ] 842
|
|
L1_PUTO [0 ] 0
|
|
L1_PUTX [2111 ] 2111
|
|
L1_PUTS_only [0 ] 0
|
|
L1_PUTS [0 ] 0
|
|
Fwd_GETX [0 ] 0
|
|
Fwd_GETS [0 ] 0
|
|
Fwd_DMA [0 ] 0
|
|
Own_GETX [0 ] 0
|
|
Inv [0 ] 0
|
|
IntAck [0 ] 0
|
|
ExtAck [0 ] 0
|
|
All_Acks [759 ] 759
|
|
Data [759 ] 759
|
|
Data_Exclusive [84 ] 84
|
|
L1_WBCLEANDATA [82 ] 82
|
|
L1_WBDIRTYDATA [806 ] 806
|
|
Writeback_Ack [833 ] 833
|
|
Writeback_Nack [0 ] 0
|
|
Unblock [0 ] 0
|
|
Exclusive_Unblock [890 ] 890
|
|
DmaAck [0 ] 0
|
|
L2_Replacement [836 ] 836
|
|
|
|
- Transitions -
|
|
NP L1_GETS [84 ] 84
|
|
NP L1_GETX [759 ] 759
|
|
NP L1_PUTO [0 ] 0
|
|
NP L1_PUTX [0 ] 0
|
|
NP L1_PUTS [0 ] 0
|
|
NP Inv [0 ] 0
|
|
|
|
I L1_GETS [0 ] 0
|
|
I L1_GETX [0 ] 0
|
|
I L1_PUTO [0 ] 0
|
|
I L1_PUTX [0 ] 0
|
|
I L1_PUTS [0 ] 0
|
|
I Inv [0 ] 0
|
|
I L2_Replacement [0 ] 0
|
|
|
|
ILS L1_GETS [0 ] 0
|
|
ILS L1_GETX [0 ] 0
|
|
ILS L1_PUTO [0 ] 0
|
|
ILS L1_PUTX [0 ] 0
|
|
ILS L1_PUTS_only [0 ] 0
|
|
ILS L1_PUTS [0 ] 0
|
|
ILS Inv [0 ] 0
|
|
ILS L2_Replacement [0 ] 0
|
|
|
|
ILX L1_GETS [0 ] 0
|
|
ILX L1_GETX [0 ] 0
|
|
ILX L1_PUTO [0 ] 0
|
|
ILX L1_PUTX [888 ] 888
|
|
ILX L1_PUTS_only [0 ] 0
|
|
ILX L1_PUTS [0 ] 0
|
|
ILX Fwd_GETX [0 ] 0
|
|
ILX Fwd_GETS [0 ] 0
|
|
ILX Fwd_DMA [0 ] 0
|
|
ILX Inv [0 ] 0
|
|
ILX Data [0 ] 0
|
|
ILX L2_Replacement [0 ] 0
|
|
|
|
ILO L1_GETS [0 ] 0
|
|
ILO L1_GETX [0 ] 0
|
|
ILO L1_PUTO [0 ] 0
|
|
ILO L1_PUTX [0 ] 0
|
|
ILO L1_PUTS [0 ] 0
|
|
ILO Fwd_GETX [0 ] 0
|
|
ILO Fwd_GETS [0 ] 0
|
|
ILO Fwd_DMA [0 ] 0
|
|
ILO Inv [0 ] 0
|
|
ILO Data [0 ] 0
|
|
ILO L2_Replacement [0 ] 0
|
|
|
|
ILOX L1_GETS [0 ] 0
|
|
ILOX L1_GETX [0 ] 0
|
|
ILOX L1_PUTO [0 ] 0
|
|
ILOX L1_PUTX [0 ] 0
|
|
ILOX L1_PUTS [0 ] 0
|
|
ILOX Fwd_GETX [0 ] 0
|
|
ILOX Fwd_GETS [0 ] 0
|
|
ILOX Fwd_DMA [0 ] 0
|
|
ILOX Data [0 ] 0
|
|
|
|
ILOS L1_GETS [0 ] 0
|
|
ILOS L1_GETX [0 ] 0
|
|
ILOS L1_PUTO [0 ] 0
|
|
ILOS L1_PUTX [0 ] 0
|
|
ILOS L1_PUTS_only [0 ] 0
|
|
ILOS L1_PUTS [0 ] 0
|
|
ILOS Fwd_GETX [0 ] 0
|
|
ILOS Fwd_GETS [0 ] 0
|
|
ILOS Fwd_DMA [0 ] 0
|
|
ILOS Data [0 ] 0
|
|
ILOS L2_Replacement [0 ] 0
|
|
|
|
ILOSX L1_GETS [0 ] 0
|
|
ILOSX L1_GETX [0 ] 0
|
|
ILOSX L1_PUTO [0 ] 0
|
|
ILOSX L1_PUTX [0 ] 0
|
|
ILOSX L1_PUTS_only [0 ] 0
|
|
ILOSX L1_PUTS [0 ] 0
|
|
ILOSX Fwd_GETX [0 ] 0
|
|
ILOSX Fwd_GETS [0 ] 0
|
|
ILOSX Fwd_DMA [0 ] 0
|
|
ILOSX Data [0 ] 0
|
|
|
|
S L1_GETS [0 ] 0
|
|
S L1_GETX [0 ] 0
|
|
S L1_PUTX [0 ] 0
|
|
S L1_PUTS [0 ] 0
|
|
S Inv [0 ] 0
|
|
S L2_Replacement [0 ] 0
|
|
|
|
O L1_GETS [0 ] 0
|
|
O L1_GETX [0 ] 0
|
|
O L1_PUTX [0 ] 0
|
|
O Fwd_GETX [0 ] 0
|
|
O Fwd_GETS [0 ] 0
|
|
O Fwd_DMA [0 ] 0
|
|
O L2_Replacement [0 ] 0
|
|
|
|
OLS L1_GETS [0 ] 0
|
|
OLS L1_GETX [0 ] 0
|
|
OLS L1_PUTX [0 ] 0
|
|
OLS L1_PUTS_only [0 ] 0
|
|
OLS L1_PUTS [0 ] 0
|
|
OLS Fwd_GETX [0 ] 0
|
|
OLS Fwd_GETS [0 ] 0
|
|
OLS Fwd_DMA [0 ] 0
|
|
OLS L2_Replacement [0 ] 0
|
|
|
|
OLSX L1_GETS [0 ] 0
|
|
OLSX L1_GETX [0 ] 0
|
|
OLSX L1_PUTO [0 ] 0
|
|
OLSX L1_PUTX [0 ] 0
|
|
OLSX L1_PUTS_only [0 ] 0
|
|
OLSX L1_PUTS [0 ] 0
|
|
OLSX Fwd_GETX [0 ] 0
|
|
OLSX Fwd_GETS [0 ] 0
|
|
OLSX Fwd_DMA [0 ] 0
|
|
OLSX L2_Replacement [0 ] 0
|
|
|
|
SLS L1_GETS [0 ] 0
|
|
SLS L1_GETX [0 ] 0
|
|
SLS L1_PUTX [0 ] 0
|
|
SLS L1_PUTS_only [0 ] 0
|
|
SLS L1_PUTS [0 ] 0
|
|
SLS Inv [0 ] 0
|
|
SLS L2_Replacement [0 ] 0
|
|
|
|
M L1_GETS [10 ] 10
|
|
M L1_GETX [40 ] 40
|
|
M L1_PUTO [0 ] 0
|
|
M L1_PUTX [0 ] 0
|
|
M L1_PUTS [0 ] 0
|
|
M Fwd_GETX [0 ] 0
|
|
M Fwd_GETS [0 ] 0
|
|
M Fwd_DMA [0 ] 0
|
|
M L2_Replacement [836 ] 836
|
|
|
|
IFGX L1_GETS [0 ] 0
|
|
IFGX L1_GETX [0 ] 0
|
|
IFGX L1_PUTO [0 ] 0
|
|
IFGX L1_PUTX [0 ] 0
|
|
IFGX L1_PUTS_only [0 ] 0
|
|
IFGX L1_PUTS [0 ] 0
|
|
IFGX Fwd_GETX [0 ] 0
|
|
IFGX Fwd_GETS [0 ] 0
|
|
IFGX Fwd_DMA [0 ] 0
|
|
IFGX Inv [0 ] 0
|
|
IFGX Data [0 ] 0
|
|
IFGX Data_Exclusive [0 ] 0
|
|
IFGX L2_Replacement [0 ] 0
|
|
|
|
IFGS L1_GETS [0 ] 0
|
|
IFGS L1_GETX [0 ] 0
|
|
IFGS L1_PUTO [0 ] 0
|
|
IFGS L1_PUTX [0 ] 0
|
|
IFGS L1_PUTS_only [0 ] 0
|
|
IFGS L1_PUTS [0 ] 0
|
|
IFGS Fwd_GETX [0 ] 0
|
|
IFGS Fwd_GETS [0 ] 0
|
|
IFGS Fwd_DMA [0 ] 0
|
|
IFGS Inv [0 ] 0
|
|
IFGS Data [0 ] 0
|
|
IFGS Data_Exclusive [0 ] 0
|
|
IFGS L2_Replacement [0 ] 0
|
|
|
|
ISFGS L1_GETS [0 ] 0
|
|
ISFGS L1_GETX [0 ] 0
|
|
ISFGS L1_PUTO [0 ] 0
|
|
ISFGS L1_PUTX [0 ] 0
|
|
ISFGS L1_PUTS_only [0 ] 0
|
|
ISFGS L1_PUTS [0 ] 0
|
|
ISFGS Fwd_GETX [0 ] 0
|
|
ISFGS Fwd_GETS [0 ] 0
|
|
ISFGS Fwd_DMA [0 ] 0
|
|
ISFGS Inv [0 ] 0
|
|
ISFGS Data [0 ] 0
|
|
ISFGS L2_Replacement [0 ] 0
|
|
|
|
IFGXX L1_GETS [0 ] 0
|
|
IFGXX L1_GETX [0 ] 0
|
|
IFGXX L1_PUTO [0 ] 0
|
|
IFGXX L1_PUTX [0 ] 0
|
|
IFGXX L1_PUTS_only [0 ] 0
|
|
IFGXX L1_PUTS [0 ] 0
|
|
IFGXX Fwd_GETX [0 ] 0
|
|
IFGXX Fwd_GETS [0 ] 0
|
|
IFGXX Fwd_DMA [0 ] 0
|
|
IFGXX Inv [0 ] 0
|
|
IFGXX IntAck [0 ] 0
|
|
IFGXX All_Acks [0 ] 0
|
|
IFGXX Data_Exclusive [0 ] 0
|
|
IFGXX L2_Replacement [0 ] 0
|
|
|
|
OFGX L1_GETS [0 ] 0
|
|
OFGX L1_GETX [0 ] 0
|
|
OFGX L1_PUTO [0 ] 0
|
|
OFGX L1_PUTX [0 ] 0
|
|
OFGX L1_PUTS_only [0 ] 0
|
|
OFGX L1_PUTS [0 ] 0
|
|
OFGX Fwd_GETX [0 ] 0
|
|
OFGX Fwd_GETS [0 ] 0
|
|
OFGX Fwd_DMA [0 ] 0
|
|
OFGX Inv [0 ] 0
|
|
OFGX L2_Replacement [0 ] 0
|
|
|
|
OLSF L1_GETS [0 ] 0
|
|
OLSF L1_GETX [0 ] 0
|
|
OLSF L1_PUTO [0 ] 0
|
|
OLSF L1_PUTX [0 ] 0
|
|
OLSF L1_PUTS_only [0 ] 0
|
|
OLSF L1_PUTS [0 ] 0
|
|
OLSF Fwd_GETX [0 ] 0
|
|
OLSF Fwd_GETS [0 ] 0
|
|
OLSF Fwd_DMA [0 ] 0
|
|
OLSF Inv [0 ] 0
|
|
OLSF IntAck [0 ] 0
|
|
OLSF All_Acks [0 ] 0
|
|
OLSF L2_Replacement [0 ] 0
|
|
|
|
ILOW L1_GETS [0 ] 0
|
|
ILOW L1_GETX [0 ] 0
|
|
ILOW L1_PUTO [0 ] 0
|
|
ILOW L1_PUTX [0 ] 0
|
|
ILOW L1_PUTS_only [0 ] 0
|
|
ILOW L1_PUTS [0 ] 0
|
|
ILOW Fwd_GETX [0 ] 0
|
|
ILOW Fwd_GETS [0 ] 0
|
|
ILOW Fwd_DMA [0 ] 0
|
|
ILOW Inv [0 ] 0
|
|
ILOW L1_WBCLEANDATA [0 ] 0
|
|
ILOW L1_WBDIRTYDATA [0 ] 0
|
|
ILOW Unblock [0 ] 0
|
|
ILOW L2_Replacement [0 ] 0
|
|
|
|
ILOXW L1_GETS [0 ] 0
|
|
ILOXW L1_GETX [0 ] 0
|
|
ILOXW L1_PUTO [0 ] 0
|
|
ILOXW L1_PUTX [0 ] 0
|
|
ILOXW L1_PUTS_only [0 ] 0
|
|
ILOXW L1_PUTS [0 ] 0
|
|
ILOXW Fwd_GETX [0 ] 0
|
|
ILOXW Fwd_GETS [0 ] 0
|
|
ILOXW Fwd_DMA [0 ] 0
|
|
ILOXW Inv [0 ] 0
|
|
ILOXW L1_WBCLEANDATA [0 ] 0
|
|
ILOXW L1_WBDIRTYDATA [0 ] 0
|
|
ILOXW Unblock [0 ] 0
|
|
ILOXW L2_Replacement [0 ] 0
|
|
|
|
ILOSW L1_GETS [0 ] 0
|
|
ILOSW L1_GETX [0 ] 0
|
|
ILOSW L1_PUTO [0 ] 0
|
|
ILOSW L1_PUTX [0 ] 0
|
|
ILOSW L1_PUTS_only [0 ] 0
|
|
ILOSW L1_PUTS [0 ] 0
|
|
ILOSW Fwd_GETX [0 ] 0
|
|
ILOSW Fwd_GETS [0 ] 0
|
|
ILOSW Fwd_DMA [0 ] 0
|
|
ILOSW Inv [0 ] 0
|
|
ILOSW L1_WBCLEANDATA [0 ] 0
|
|
ILOSW L1_WBDIRTYDATA [0 ] 0
|
|
ILOSW Unblock [0 ] 0
|
|
ILOSW L2_Replacement [0 ] 0
|
|
|
|
ILOSXW L1_GETS [0 ] 0
|
|
ILOSXW L1_GETX [0 ] 0
|
|
ILOSXW L1_PUTO [0 ] 0
|
|
ILOSXW L1_PUTX [0 ] 0
|
|
ILOSXW L1_PUTS_only [0 ] 0
|
|
ILOSXW L1_PUTS [0 ] 0
|
|
ILOSXW Fwd_GETX [0 ] 0
|
|
ILOSXW Fwd_GETS [0 ] 0
|
|
ILOSXW Fwd_DMA [0 ] 0
|
|
ILOSXW Inv [0 ] 0
|
|
ILOSXW L1_WBCLEANDATA [0 ] 0
|
|
ILOSXW L1_WBDIRTYDATA [0 ] 0
|
|
ILOSXW Unblock [0 ] 0
|
|
ILOSXW L2_Replacement [0 ] 0
|
|
|
|
SLSW L1_GETS [0 ] 0
|
|
SLSW L1_GETX [0 ] 0
|
|
SLSW L1_PUTO [0 ] 0
|
|
SLSW L1_PUTX [0 ] 0
|
|
SLSW L1_PUTS_only [0 ] 0
|
|
SLSW L1_PUTS [0 ] 0
|
|
SLSW Fwd_GETX [0 ] 0
|
|
SLSW Fwd_GETS [0 ] 0
|
|
SLSW Fwd_DMA [0 ] 0
|
|
SLSW Inv [0 ] 0
|
|
SLSW Unblock [0 ] 0
|
|
SLSW L2_Replacement [0 ] 0
|
|
|
|
OLSW L1_GETS [0 ] 0
|
|
OLSW L1_GETX [0 ] 0
|
|
OLSW L1_PUTO [0 ] 0
|
|
OLSW L1_PUTX [0 ] 0
|
|
OLSW L1_PUTS_only [0 ] 0
|
|
OLSW L1_PUTS [0 ] 0
|
|
OLSW Fwd_GETX [0 ] 0
|
|
OLSW Fwd_GETS [0 ] 0
|
|
OLSW Fwd_DMA [0 ] 0
|
|
OLSW Inv [0 ] 0
|
|
OLSW Unblock [0 ] 0
|
|
OLSW L2_Replacement [0 ] 0
|
|
|
|
ILSW L1_GETS [0 ] 0
|
|
ILSW L1_GETX [0 ] 0
|
|
ILSW L1_PUTO [0 ] 0
|
|
ILSW L1_PUTX [0 ] 0
|
|
ILSW L1_PUTS_only [0 ] 0
|
|
ILSW L1_PUTS [0 ] 0
|
|
ILSW Fwd_GETX [0 ] 0
|
|
ILSW Fwd_GETS [0 ] 0
|
|
ILSW Fwd_DMA [0 ] 0
|
|
ILSW Inv [0 ] 0
|
|
ILSW L1_WBCLEANDATA [0 ] 0
|
|
ILSW Unblock [0 ] 0
|
|
ILSW L2_Replacement [0 ] 0
|
|
|
|
IW L1_GETS [0 ] 0
|
|
IW L1_GETX [0 ] 0
|
|
IW L1_PUTO [0 ] 0
|
|
IW L1_PUTX [0 ] 0
|
|
IW L1_PUTS_only [0 ] 0
|
|
IW L1_PUTS [0 ] 0
|
|
IW Fwd_GETX [0 ] 0
|
|
IW Fwd_GETS [0 ] 0
|
|
IW Fwd_DMA [0 ] 0
|
|
IW Inv [0 ] 0
|
|
IW L1_WBCLEANDATA [0 ] 0
|
|
IW L2_Replacement [0 ] 0
|
|
|
|
OW L1_GETS [0 ] 0
|
|
OW L1_GETX [0 ] 0
|
|
OW L1_PUTO [0 ] 0
|
|
OW L1_PUTX [0 ] 0
|
|
OW L1_PUTS_only [0 ] 0
|
|
OW L1_PUTS [0 ] 0
|
|
OW Fwd_GETX [0 ] 0
|
|
OW Fwd_GETS [0 ] 0
|
|
OW Fwd_DMA [0 ] 0
|
|
OW Inv [0 ] 0
|
|
OW Unblock [0 ] 0
|
|
OW L2_Replacement [0 ] 0
|
|
|
|
SW L1_GETS [0 ] 0
|
|
SW L1_GETX [0 ] 0
|
|
SW L1_PUTO [0 ] 0
|
|
SW L1_PUTX [0 ] 0
|
|
SW L1_PUTS_only [0 ] 0
|
|
SW L1_PUTS [0 ] 0
|
|
SW Fwd_GETX [0 ] 0
|
|
SW Fwd_GETS [0 ] 0
|
|
SW Fwd_DMA [0 ] 0
|
|
SW Inv [0 ] 0
|
|
SW Unblock [0 ] 0
|
|
SW L2_Replacement [0 ] 0
|
|
|
|
OXW L1_GETS [0 ] 0
|
|
OXW L1_GETX [0 ] 0
|
|
OXW L1_PUTO [0 ] 0
|
|
OXW L1_PUTX [0 ] 0
|
|
OXW L1_PUTS_only [0 ] 0
|
|
OXW L1_PUTS [0 ] 0
|
|
OXW Fwd_GETX [0 ] 0
|
|
OXW Fwd_GETS [0 ] 0
|
|
OXW Fwd_DMA [0 ] 0
|
|
OXW Inv [0 ] 0
|
|
OXW Unblock [0 ] 0
|
|
OXW L2_Replacement [0 ] 0
|
|
|
|
OLSXW L1_GETS [0 ] 0
|
|
OLSXW L1_GETX [0 ] 0
|
|
OLSXW L1_PUTO [0 ] 0
|
|
OLSXW L1_PUTX [0 ] 0
|
|
OLSXW L1_PUTS_only [0 ] 0
|
|
OLSXW L1_PUTS [0 ] 0
|
|
OLSXW Fwd_GETX [0 ] 0
|
|
OLSXW Fwd_GETS [0 ] 0
|
|
OLSXW Fwd_DMA [0 ] 0
|
|
OLSXW Inv [0 ] 0
|
|
OLSXW Unblock [0 ] 0
|
|
OLSXW L2_Replacement [0 ] 0
|
|
|
|
ILXW L1_GETS [63 ] 63
|
|
ILXW L1_GETX [23 ] 23
|
|
ILXW L1_PUTO [0 ] 0
|
|
ILXW L1_PUTX [0 ] 0
|
|
ILXW L1_PUTS_only [0 ] 0
|
|
ILXW L1_PUTS [0 ] 0
|
|
ILXW Fwd_GETX [0 ] 0
|
|
ILXW Fwd_GETS [0 ] 0
|
|
ILXW Fwd_DMA [0 ] 0
|
|
ILXW Inv [0 ] 0
|
|
ILXW Data [0 ] 0
|
|
ILXW L1_WBCLEANDATA [82 ] 82
|
|
ILXW L1_WBDIRTYDATA [806 ] 806
|
|
ILXW Unblock [0 ] 0
|
|
ILXW L2_Replacement [0 ] 0
|
|
|
|
IFLS L1_GETS [0 ] 0
|
|
IFLS L1_GETX [0 ] 0
|
|
IFLS L1_PUTO [0 ] 0
|
|
IFLS L1_PUTX [0 ] 0
|
|
IFLS L1_PUTS_only [0 ] 0
|
|
IFLS L1_PUTS [0 ] 0
|
|
IFLS Fwd_GETX [0 ] 0
|
|
IFLS Fwd_GETS [0 ] 0
|
|
IFLS Fwd_DMA [0 ] 0
|
|
IFLS Inv [0 ] 0
|
|
IFLS Unblock [0 ] 0
|
|
IFLS L2_Replacement [0 ] 0
|
|
|
|
IFLO L1_GETS [0 ] 0
|
|
IFLO L1_GETX [0 ] 0
|
|
IFLO L1_PUTO [0 ] 0
|
|
IFLO L1_PUTX [0 ] 0
|
|
IFLO L1_PUTS_only [0 ] 0
|
|
IFLO L1_PUTS [0 ] 0
|
|
IFLO Fwd_GETX [0 ] 0
|
|
IFLO Fwd_GETS [0 ] 0
|
|
IFLO Fwd_DMA [0 ] 0
|
|
IFLO Inv [0 ] 0
|
|
IFLO Unblock [0 ] 0
|
|
IFLO L2_Replacement [0 ] 0
|
|
|
|
IFLOX L1_GETS [0 ] 0
|
|
IFLOX L1_GETX [0 ] 0
|
|
IFLOX L1_PUTO [0 ] 0
|
|
IFLOX L1_PUTX [0 ] 0
|
|
IFLOX L1_PUTS_only [0 ] 0
|
|
IFLOX L1_PUTS [0 ] 0
|
|
IFLOX Fwd_GETX [0 ] 0
|
|
IFLOX Fwd_GETS [0 ] 0
|
|
IFLOX Fwd_DMA [0 ] 0
|
|
IFLOX Inv [0 ] 0
|
|
IFLOX Unblock [0 ] 0
|
|
IFLOX Exclusive_Unblock [0 ] 0
|
|
IFLOX L2_Replacement [0 ] 0
|
|
|
|
IFLOXX L1_GETS [0 ] 0
|
|
IFLOXX L1_GETX [0 ] 0
|
|
IFLOXX L1_PUTO [0 ] 0
|
|
IFLOXX L1_PUTX [0 ] 0
|
|
IFLOXX L1_PUTS_only [0 ] 0
|
|
IFLOXX L1_PUTS [0 ] 0
|
|
IFLOXX Fwd_GETX [0 ] 0
|
|
IFLOXX Fwd_GETS [0 ] 0
|
|
IFLOXX Fwd_DMA [0 ] 0
|
|
IFLOXX Inv [0 ] 0
|
|
IFLOXX Unblock [0 ] 0
|
|
IFLOXX Exclusive_Unblock [0 ] 0
|
|
IFLOXX L2_Replacement [0 ] 0
|
|
|
|
IFLOSX L1_GETS [0 ] 0
|
|
IFLOSX L1_GETX [0 ] 0
|
|
IFLOSX L1_PUTO [0 ] 0
|
|
IFLOSX L1_PUTX [0 ] 0
|
|
IFLOSX L1_PUTS_only [0 ] 0
|
|
IFLOSX L1_PUTS [0 ] 0
|
|
IFLOSX Fwd_GETX [0 ] 0
|
|
IFLOSX Fwd_GETS [0 ] 0
|
|
IFLOSX Fwd_DMA [0 ] 0
|
|
IFLOSX Inv [0 ] 0
|
|
IFLOSX Unblock [0 ] 0
|
|
IFLOSX Exclusive_Unblock [0 ] 0
|
|
IFLOSX L2_Replacement [0 ] 0
|
|
|
|
IFLXO L1_GETS [0 ] 0
|
|
IFLXO L1_GETX [0 ] 0
|
|
IFLXO L1_PUTO [0 ] 0
|
|
IFLXO L1_PUTX [0 ] 0
|
|
IFLXO L1_PUTS_only [0 ] 0
|
|
IFLXO L1_PUTS [0 ] 0
|
|
IFLXO Fwd_GETX [0 ] 0
|
|
IFLXO Fwd_GETS [0 ] 0
|
|
IFLXO Fwd_DMA [0 ] 0
|
|
IFLXO Inv [0 ] 0
|
|
IFLXO Exclusive_Unblock [0 ] 0
|
|
IFLXO L2_Replacement [0 ] 0
|
|
|
|
IGS L1_GETS [0 ] 0
|
|
IGS L1_GETX [0 ] 0
|
|
IGS L1_PUTO [0 ] 0
|
|
IGS L1_PUTX [99 ] 99
|
|
IGS L1_PUTS_only [0 ] 0
|
|
IGS L1_PUTS [0 ] 0
|
|
IGS Fwd_GETX [0 ] 0
|
|
IGS Fwd_GETS [0 ] 0
|
|
IGS Fwd_DMA [0 ] 0
|
|
IGS Own_GETX [0 ] 0
|
|
IGS Inv [0 ] 0
|
|
IGS Data [0 ] 0
|
|
IGS Data_Exclusive [84 ] 84
|
|
IGS Unblock [0 ] 0
|
|
IGS Exclusive_Unblock [83 ] 83
|
|
IGS L2_Replacement [0 ] 0
|
|
|
|
IGM L1_GETS [0 ] 0
|
|
IGM L1_GETX [0 ] 0
|
|
IGM L1_PUTO [0 ] 0
|
|
IGM L1_PUTX [0 ] 0
|
|
IGM L1_PUTS_only [0 ] 0
|
|
IGM L1_PUTS [0 ] 0
|
|
IGM Fwd_GETX [0 ] 0
|
|
IGM Fwd_GETS [0 ] 0
|
|
IGM Fwd_DMA [0 ] 0
|
|
IGM Own_GETX [0 ] 0
|
|
IGM Inv [0 ] 0
|
|
IGM ExtAck [0 ] 0
|
|
IGM Data [759 ] 759
|
|
IGM Data_Exclusive [0 ] 0
|
|
IGM L2_Replacement [0 ] 0
|
|
|
|
IGMLS L1_GETS [0 ] 0
|
|
IGMLS L1_GETX [0 ] 0
|
|
IGMLS L1_PUTO [0 ] 0
|
|
IGMLS L1_PUTX [0 ] 0
|
|
IGMLS L1_PUTS_only [0 ] 0
|
|
IGMLS L1_PUTS [0 ] 0
|
|
IGMLS Inv [0 ] 0
|
|
IGMLS IntAck [0 ] 0
|
|
IGMLS ExtAck [0 ] 0
|
|
IGMLS All_Acks [0 ] 0
|
|
IGMLS Data [0 ] 0
|
|
IGMLS Data_Exclusive [0 ] 0
|
|
IGMLS L2_Replacement [0 ] 0
|
|
|
|
IGMO L1_GETS [0 ] 0
|
|
IGMO L1_GETX [0 ] 0
|
|
IGMO L1_PUTO [0 ] 0
|
|
IGMO L1_PUTX [1113 ] 1113
|
|
IGMO L1_PUTS_only [0 ] 0
|
|
IGMO L1_PUTS [0 ] 0
|
|
IGMO Fwd_GETX [0 ] 0
|
|
IGMO Fwd_GETS [0 ] 0
|
|
IGMO Fwd_DMA [0 ] 0
|
|
IGMO Own_GETX [0 ] 0
|
|
IGMO ExtAck [0 ] 0
|
|
IGMO All_Acks [759 ] 759
|
|
IGMO Exclusive_Unblock [758 ] 758
|
|
IGMO L2_Replacement [0 ] 0
|
|
|
|
IGMIO L1_GETS [0 ] 0
|
|
IGMIO L1_GETX [0 ] 0
|
|
IGMIO L1_PUTO [0 ] 0
|
|
IGMIO L1_PUTX [0 ] 0
|
|
IGMIO L1_PUTS_only [0 ] 0
|
|
IGMIO L1_PUTS [0 ] 0
|
|
IGMIO Fwd_GETX [0 ] 0
|
|
IGMIO Fwd_GETS [0 ] 0
|
|
IGMIO Fwd_DMA [0 ] 0
|
|
IGMIO Own_GETX [0 ] 0
|
|
IGMIO ExtAck [0 ] 0
|
|
IGMIO All_Acks [0 ] 0
|
|
|
|
OGMIO L1_GETS [0 ] 0
|
|
OGMIO L1_GETX [0 ] 0
|
|
OGMIO L1_PUTO [0 ] 0
|
|
OGMIO L1_PUTX [0 ] 0
|
|
OGMIO L1_PUTS_only [0 ] 0
|
|
OGMIO L1_PUTS [0 ] 0
|
|
OGMIO Fwd_GETX [0 ] 0
|
|
OGMIO Fwd_GETS [0 ] 0
|
|
OGMIO Fwd_DMA [0 ] 0
|
|
OGMIO Own_GETX [0 ] 0
|
|
OGMIO ExtAck [0 ] 0
|
|
OGMIO All_Acks [0 ] 0
|
|
|
|
IGMIOF L1_GETS [0 ] 0
|
|
IGMIOF L1_GETX [0 ] 0
|
|
IGMIOF L1_PUTO [0 ] 0
|
|
IGMIOF L1_PUTX [0 ] 0
|
|
IGMIOF L1_PUTS_only [0 ] 0
|
|
IGMIOF L1_PUTS [0 ] 0
|
|
IGMIOF IntAck [0 ] 0
|
|
IGMIOF All_Acks [0 ] 0
|
|
IGMIOF Data_Exclusive [0 ] 0
|
|
|
|
IGMIOFS L1_GETS [0 ] 0
|
|
IGMIOFS L1_GETX [0 ] 0
|
|
IGMIOFS L1_PUTO [0 ] 0
|
|
IGMIOFS L1_PUTX [0 ] 0
|
|
IGMIOFS L1_PUTS_only [0 ] 0
|
|
IGMIOFS L1_PUTS [0 ] 0
|
|
IGMIOFS Fwd_GETX [0 ] 0
|
|
IGMIOFS Fwd_GETS [0 ] 0
|
|
IGMIOFS Fwd_DMA [0 ] 0
|
|
IGMIOFS Inv [0 ] 0
|
|
IGMIOFS Data [0 ] 0
|
|
IGMIOFS L2_Replacement [0 ] 0
|
|
|
|
OGMIOF L1_GETS [0 ] 0
|
|
OGMIOF L1_GETX [0 ] 0
|
|
OGMIOF L1_PUTO [0 ] 0
|
|
OGMIOF L1_PUTX [0 ] 0
|
|
OGMIOF L1_PUTS_only [0 ] 0
|
|
OGMIOF L1_PUTS [0 ] 0
|
|
OGMIOF IntAck [0 ] 0
|
|
OGMIOF All_Acks [0 ] 0
|
|
|
|
II L1_GETS [0 ] 0
|
|
II L1_GETX [0 ] 0
|
|
II L1_PUTO [0 ] 0
|
|
II L1_PUTX [0 ] 0
|
|
II L1_PUTS_only [0 ] 0
|
|
II L1_PUTS [0 ] 0
|
|
II IntAck [0 ] 0
|
|
II All_Acks [0 ] 0
|
|
|
|
MM L1_GETS [0 ] 0
|
|
MM L1_GETX [0 ] 0
|
|
MM L1_PUTO [0 ] 0
|
|
MM L1_PUTX [11 ] 11
|
|
MM L1_PUTS_only [0 ] 0
|
|
MM L1_PUTS [0 ] 0
|
|
MM Fwd_GETX [0 ] 0
|
|
MM Fwd_GETS [0 ] 0
|
|
MM Fwd_DMA [0 ] 0
|
|
MM Inv [0 ] 0
|
|
MM Exclusive_Unblock [40 ] 40
|
|
MM L2_Replacement [0 ] 0
|
|
|
|
SS L1_GETS [0 ] 0
|
|
SS L1_GETX [0 ] 0
|
|
SS L1_PUTO [0 ] 0
|
|
SS L1_PUTX [0 ] 0
|
|
SS L1_PUTS_only [0 ] 0
|
|
SS L1_PUTS [0 ] 0
|
|
SS Fwd_GETX [0 ] 0
|
|
SS Fwd_GETS [0 ] 0
|
|
SS Fwd_DMA [0 ] 0
|
|
SS Inv [0 ] 0
|
|
SS Unblock [0 ] 0
|
|
SS L2_Replacement [0 ] 0
|
|
|
|
OO L1_GETS [0 ] 0
|
|
OO L1_GETX [0 ] 0
|
|
OO L1_PUTO [0 ] 0
|
|
OO L1_PUTX [0 ] 0
|
|
OO L1_PUTS_only [0 ] 0
|
|
OO L1_PUTS [0 ] 0
|
|
OO Fwd_GETX [0 ] 0
|
|
OO Fwd_GETS [0 ] 0
|
|
OO Fwd_DMA [0 ] 0
|
|
OO Inv [0 ] 0
|
|
OO Unblock [0 ] 0
|
|
OO Exclusive_Unblock [9 ] 9
|
|
OO L2_Replacement [0 ] 0
|
|
|
|
OLSS L1_GETS [0 ] 0
|
|
OLSS L1_GETX [0 ] 0
|
|
OLSS L1_PUTO [0 ] 0
|
|
OLSS L1_PUTX [0 ] 0
|
|
OLSS L1_PUTS_only [0 ] 0
|
|
OLSS L1_PUTS [0 ] 0
|
|
OLSS Fwd_GETX [0 ] 0
|
|
OLSS Fwd_GETS [0 ] 0
|
|
OLSS Fwd_DMA [0 ] 0
|
|
OLSS Inv [0 ] 0
|
|
OLSS Unblock [0 ] 0
|
|
OLSS L2_Replacement [0 ] 0
|
|
|
|
OLSXS L1_GETS [0 ] 0
|
|
OLSXS L1_GETX [0 ] 0
|
|
OLSXS L1_PUTO [0 ] 0
|
|
OLSXS L1_PUTX [0 ] 0
|
|
OLSXS L1_PUTS_only [0 ] 0
|
|
OLSXS L1_PUTS [0 ] 0
|
|
OLSXS Fwd_GETX [0 ] 0
|
|
OLSXS Fwd_GETS [0 ] 0
|
|
OLSXS Fwd_DMA [0 ] 0
|
|
OLSXS Inv [0 ] 0
|
|
OLSXS Unblock [0 ] 0
|
|
OLSXS L2_Replacement [0 ] 0
|
|
|
|
SLSS L1_GETS [0 ] 0
|
|
SLSS L1_GETX [0 ] 0
|
|
SLSS L1_PUTO [0 ] 0
|
|
SLSS L1_PUTX [0 ] 0
|
|
SLSS L1_PUTS_only [0 ] 0
|
|
SLSS L1_PUTS [0 ] 0
|
|
SLSS Fwd_GETX [0 ] 0
|
|
SLSS Fwd_GETS [0 ] 0
|
|
SLSS Fwd_DMA [0 ] 0
|
|
SLSS Inv [0 ] 0
|
|
SLSS Unblock [0 ] 0
|
|
SLSS L2_Replacement [0 ] 0
|
|
|
|
OI L1_GETS [0 ] 0
|
|
OI L1_GETX [0 ] 0
|
|
OI L1_PUTO [0 ] 0
|
|
OI L1_PUTX [0 ] 0
|
|
OI L1_PUTS_only [0 ] 0
|
|
OI L1_PUTS [0 ] 0
|
|
OI Fwd_GETX [0 ] 0
|
|
OI Fwd_GETS [0 ] 0
|
|
OI Fwd_DMA [0 ] 0
|
|
OI Writeback_Ack [0 ] 0
|
|
OI Writeback_Nack [0 ] 0
|
|
OI L2_Replacement [0 ] 0
|
|
|
|
MI L1_GETS [0 ] 0
|
|
MI L1_GETX [20 ] 20
|
|
MI L1_PUTO [0 ] 0
|
|
MI L1_PUTX [0 ] 0
|
|
MI L1_PUTS_only [0 ] 0
|
|
MI L1_PUTS [0 ] 0
|
|
MI Fwd_GETX [0 ] 0
|
|
MI Fwd_GETS [0 ] 0
|
|
MI Fwd_DMA [0 ] 0
|
|
MI Writeback_Ack [833 ] 833
|
|
MI L2_Replacement [0 ] 0
|
|
|
|
MII L1_GETS [0 ] 0
|
|
MII L1_GETX [0 ] 0
|
|
MII L1_PUTO [0 ] 0
|
|
MII L1_PUTX [0 ] 0
|
|
MII L1_PUTS_only [0 ] 0
|
|
MII L1_PUTS [0 ] 0
|
|
MII Writeback_Ack [0 ] 0
|
|
MII Writeback_Nack [0 ] 0
|
|
MII L2_Replacement [0 ] 0
|
|
|
|
OLSI L1_GETS [0 ] 0
|
|
OLSI L1_GETX [0 ] 0
|
|
OLSI L1_PUTO [0 ] 0
|
|
OLSI L1_PUTX [0 ] 0
|
|
OLSI L1_PUTS_only [0 ] 0
|
|
OLSI L1_PUTS [0 ] 0
|
|
OLSI Fwd_GETX [0 ] 0
|
|
OLSI Fwd_GETS [0 ] 0
|
|
OLSI Fwd_DMA [0 ] 0
|
|
OLSI Writeback_Ack [0 ] 0
|
|
OLSI L2_Replacement [0 ] 0
|
|
|
|
ILSI L1_GETS [0 ] 0
|
|
ILSI L1_GETX [0 ] 0
|
|
ILSI L1_PUTO [0 ] 0
|
|
ILSI L1_PUTX [0 ] 0
|
|
ILSI L1_PUTS_only [0 ] 0
|
|
ILSI L1_PUTS [0 ] 0
|
|
ILSI IntAck [0 ] 0
|
|
ILSI All_Acks [0 ] 0
|
|
ILSI Writeback_Ack [0 ] 0
|
|
ILSI L2_Replacement [0 ] 0
|
|
|
|
ILOSD L1_GETS [0 ] 0
|
|
ILOSD L1_GETX [0 ] 0
|
|
ILOSD L1_PUTO [0 ] 0
|
|
ILOSD L1_PUTX [0 ] 0
|
|
ILOSD L1_PUTS_only [0 ] 0
|
|
ILOSD L1_PUTS [0 ] 0
|
|
ILOSD Fwd_GETX [0 ] 0
|
|
ILOSD Fwd_GETS [0 ] 0
|
|
ILOSD Fwd_DMA [0 ] 0
|
|
ILOSD Own_GETX [0 ] 0
|
|
ILOSD Inv [0 ] 0
|
|
ILOSD DmaAck [0 ] 0
|
|
ILOSD L2_Replacement [0 ] 0
|
|
|
|
ILOSXD L1_GETS [0 ] 0
|
|
ILOSXD L1_GETX [0 ] 0
|
|
ILOSXD L1_PUTO [0 ] 0
|
|
ILOSXD L1_PUTX [0 ] 0
|
|
ILOSXD L1_PUTS_only [0 ] 0
|
|
ILOSXD L1_PUTS [0 ] 0
|
|
ILOSXD Fwd_GETX [0 ] 0
|
|
ILOSXD Fwd_GETS [0 ] 0
|
|
ILOSXD Fwd_DMA [0 ] 0
|
|
ILOSXD Own_GETX [0 ] 0
|
|
ILOSXD Inv [0 ] 0
|
|
ILOSXD DmaAck [0 ] 0
|
|
ILOSXD L2_Replacement [0 ] 0
|
|
|
|
ILOD L1_GETS [0 ] 0
|
|
ILOD L1_GETX [0 ] 0
|
|
ILOD L1_PUTO [0 ] 0
|
|
ILOD L1_PUTX [0 ] 0
|
|
ILOD L1_PUTS_only [0 ] 0
|
|
ILOD L1_PUTS [0 ] 0
|
|
ILOD Fwd_GETX [0 ] 0
|
|
ILOD Fwd_GETS [0 ] 0
|
|
ILOD Fwd_DMA [0 ] 0
|
|
ILOD Own_GETX [0 ] 0
|
|
ILOD Inv [0 ] 0
|
|
ILOD DmaAck [0 ] 0
|
|
ILOD L2_Replacement [0 ] 0
|
|
|
|
ILXD L1_GETS [0 ] 0
|
|
ILXD L1_GETX [0 ] 0
|
|
ILXD L1_PUTO [0 ] 0
|
|
ILXD L1_PUTX [0 ] 0
|
|
ILXD L1_PUTS_only [0 ] 0
|
|
ILXD L1_PUTS [0 ] 0
|
|
ILXD Fwd_GETX [0 ] 0
|
|
ILXD Fwd_GETS [0 ] 0
|
|
ILXD Fwd_DMA [0 ] 0
|
|
ILXD Own_GETX [0 ] 0
|
|
ILXD Inv [0 ] 0
|
|
ILXD DmaAck [0 ] 0
|
|
ILXD L2_Replacement [0 ] 0
|
|
|
|
ILOXD L1_GETS [0 ] 0
|
|
ILOXD L1_GETX [0 ] 0
|
|
ILOXD L1_PUTO [0 ] 0
|
|
ILOXD L1_PUTX [0 ] 0
|
|
ILOXD L1_PUTS_only [0 ] 0
|
|
ILOXD L1_PUTS [0 ] 0
|
|
ILOXD Fwd_GETX [0 ] 0
|
|
ILOXD Fwd_GETS [0 ] 0
|
|
ILOXD Fwd_DMA [0 ] 0
|
|
ILOXD Own_GETX [0 ] 0
|
|
ILOXD Inv [0 ] 0
|
|
ILOXD DmaAck [0 ] 0
|
|
ILOXD L2_Replacement [0 ] 0
|
|
|
|
Memory controller: system.dir_cntrl0.memBuffer:
|
|
memory_total_requests: 1598
|
|
memory_reads: 843
|
|
memory_writes: 755
|
|
memory_refreshes: 774
|
|
memory_total_request_delays: 711
|
|
memory_delays_per_request: 0.444931
|
|
memory_delays_in_input_queue: 99
|
|
memory_delays_behind_head_of_bank_queue: 1
|
|
memory_delays_stalled_at_head_of_bank_queue: 611
|
|
memory_stalls_for_bank_busy: 192
|
|
memory_stalls_for_random_busy: 0
|
|
memory_stalls_for_anti_starvation: 0
|
|
memory_stalls_for_arbitration: 42
|
|
memory_stalls_for_bus: 230
|
|
memory_stalls_for_tfaw: 0
|
|
memory_stalls_for_read_write_turnaround: 69
|
|
memory_stalls_for_read_read_turnaround: 78
|
|
accesses_per_bank: 55 50 42 77 67 66 60 47 44 55 47 36 56 64 44 42 45 36 61 44 58 41 44 55 46 43 43 50 49 41 48 42
|
|
|
|
--- Directory ---
|
|
- Event Counts -
|
|
GETX [761 ] 761
|
|
GETS [84 ] 84
|
|
PUTX [834 ] 834
|
|
PUTO [0 ] 0
|
|
PUTO_SHARERS [0 ] 0
|
|
Unblock [0 ] 0
|
|
Last_Unblock [0 ] 0
|
|
Exclusive_Unblock [841 ] 841
|
|
Clean_Writeback [78 ] 78
|
|
Dirty_Writeback [755 ] 755
|
|
Memory_Data [843 ] 843
|
|
Memory_Ack [754 ] 754
|
|
DMA_READ [0 ] 0
|
|
DMA_WRITE [0 ] 0
|
|
DMA_ACK [0 ] 0
|
|
Data [0 ] 0
|
|
|
|
- Transitions -
|
|
I GETX [759 ] 759
|
|
I GETS [84 ] 84
|
|
I PUTX [0 ] 0
|
|
I PUTO [0 ] 0
|
|
I Memory_Data [0 ] 0
|
|
I Memory_Ack [750 ] 750
|
|
I DMA_READ [0 ] 0
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
S GETX [0 ] 0
|
|
S GETS [0 ] 0
|
|
S PUTX [0 ] 0
|
|
S PUTO [0 ] 0
|
|
S Memory_Data [0 ] 0
|
|
S Memory_Ack [0 ] 0
|
|
S DMA_READ [0 ] 0
|
|
S DMA_WRITE [0 ] 0
|
|
|
|
O GETX [0 ] 0
|
|
O GETS [0 ] 0
|
|
O PUTX [0 ] 0
|
|
O PUTO [0 ] 0
|
|
O PUTO_SHARERS [0 ] 0
|
|
O Memory_Data [0 ] 0
|
|
O Memory_Ack [0 ] 0
|
|
O DMA_READ [0 ] 0
|
|
O DMA_WRITE [0 ] 0
|
|
|
|
M GETX [0 ] 0
|
|
M GETS [0 ] 0
|
|
M PUTX [834 ] 834
|
|
M PUTO [0 ] 0
|
|
M PUTO_SHARERS [0 ] 0
|
|
M Memory_Data [0 ] 0
|
|
M Memory_Ack [0 ] 0
|
|
M DMA_READ [0 ] 0
|
|
M DMA_WRITE [0 ] 0
|
|
|
|
IS GETX [0 ] 0
|
|
IS GETS [0 ] 0
|
|
IS PUTX [0 ] 0
|
|
IS PUTO [0 ] 0
|
|
IS PUTO_SHARERS [0 ] 0
|
|
IS Unblock [0 ] 0
|
|
IS Exclusive_Unblock [83 ] 83
|
|
IS Memory_Data [84 ] 84
|
|
IS Memory_Ack [1 ] 1
|
|
IS DMA_READ [0 ] 0
|
|
IS DMA_WRITE [0 ] 0
|
|
|
|
SS GETX [0 ] 0
|
|
SS GETS [0 ] 0
|
|
SS PUTX [0 ] 0
|
|
SS PUTO [0 ] 0
|
|
SS PUTO_SHARERS [0 ] 0
|
|
SS Unblock [0 ] 0
|
|
SS Last_Unblock [0 ] 0
|
|
SS Memory_Data [0 ] 0
|
|
SS Memory_Ack [0 ] 0
|
|
SS DMA_READ [0 ] 0
|
|
SS DMA_WRITE [0 ] 0
|
|
|
|
OO GETX [0 ] 0
|
|
OO GETS [0 ] 0
|
|
OO PUTX [0 ] 0
|
|
OO PUTO [0 ] 0
|
|
OO PUTO_SHARERS [0 ] 0
|
|
OO Unblock [0 ] 0
|
|
OO Last_Unblock [0 ] 0
|
|
OO Memory_Data [0 ] 0
|
|
OO Memory_Ack [0 ] 0
|
|
OO DMA_READ [0 ] 0
|
|
OO DMA_WRITE [0 ] 0
|
|
|
|
MO GETX [0 ] 0
|
|
MO GETS [0 ] 0
|
|
MO PUTX [0 ] 0
|
|
MO PUTO [0 ] 0
|
|
MO PUTO_SHARERS [0 ] 0
|
|
MO Unblock [0 ] 0
|
|
MO Exclusive_Unblock [0 ] 0
|
|
MO Memory_Data [0 ] 0
|
|
MO Memory_Ack [0 ] 0
|
|
MO DMA_READ [0 ] 0
|
|
MO DMA_WRITE [0 ] 0
|
|
|
|
MM GETX [0 ] 0
|
|
MM GETS [0 ] 0
|
|
MM PUTX [0 ] 0
|
|
MM PUTO [0 ] 0
|
|
MM PUTO_SHARERS [0 ] 0
|
|
MM Exclusive_Unblock [758 ] 758
|
|
MM Memory_Data [759 ] 759
|
|
MM Memory_Ack [3 ] 3
|
|
MM DMA_READ [0 ] 0
|
|
MM DMA_WRITE [0 ] 0
|
|
|
|
|
|
MI GETX [2 ] 2
|
|
MI GETS [0 ] 0
|
|
MI PUTX [0 ] 0
|
|
MI PUTO [0 ] 0
|
|
MI PUTO_SHARERS [0 ] 0
|
|
MI Unblock [0 ] 0
|
|
MI Clean_Writeback [78 ] 78
|
|
MI Dirty_Writeback [755 ] 755
|
|
MI Memory_Data [0 ] 0
|
|
MI Memory_Ack [0 ] 0
|
|
MI DMA_READ [0 ] 0
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
MIS GETX [0 ] 0
|
|
MIS GETS [0 ] 0
|
|
MIS PUTX [0 ] 0
|
|
MIS PUTO [0 ] 0
|
|
MIS PUTO_SHARERS [0 ] 0
|
|
MIS Unblock [0 ] 0
|
|
MIS Clean_Writeback [0 ] 0
|
|
MIS Dirty_Writeback [0 ] 0
|
|
MIS Memory_Data [0 ] 0
|
|
MIS Memory_Ack [0 ] 0
|
|
MIS DMA_READ [0 ] 0
|
|
MIS DMA_WRITE [0 ] 0
|
|
|
|
OS GETX [0 ] 0
|
|
OS GETS [0 ] 0
|
|
OS PUTX [0 ] 0
|
|
OS PUTO [0 ] 0
|
|
OS PUTO_SHARERS [0 ] 0
|
|
OS Unblock [0 ] 0
|
|
OS Clean_Writeback [0 ] 0
|
|
OS Dirty_Writeback [0 ] 0
|
|
OS Memory_Data [0 ] 0
|
|
OS Memory_Ack [0 ] 0
|
|
OS DMA_READ [0 ] 0
|
|
OS DMA_WRITE [0 ] 0
|
|
|
|
OSS GETX [0 ] 0
|
|
OSS GETS [0 ] 0
|
|
OSS PUTX [0 ] 0
|
|
OSS PUTO [0 ] 0
|
|
OSS PUTO_SHARERS [0 ] 0
|
|
OSS Unblock [0 ] 0
|
|
OSS Clean_Writeback [0 ] 0
|
|
OSS Dirty_Writeback [0 ] 0
|
|
OSS Memory_Data [0 ] 0
|
|
OSS Memory_Ack [0 ] 0
|
|
OSS DMA_READ [0 ] 0
|
|
OSS DMA_WRITE [0 ] 0
|
|
|
|
XI_M GETX [0 ] 0
|
|
XI_M GETS [0 ] 0
|
|
XI_M PUTX [0 ] 0
|
|
XI_M PUTO [0 ] 0
|
|
XI_M PUTO_SHARERS [0 ] 0
|
|
XI_M Memory_Data [0 ] 0
|
|
XI_M Memory_Ack [0 ] 0
|
|
XI_M DMA_READ [0 ] 0
|
|
XI_M DMA_WRITE [0 ] 0
|
|
|
|
XI_U GETX [0 ] 0
|
|
XI_U GETS [0 ] 0
|
|
XI_U PUTX [0 ] 0
|
|
XI_U PUTO [0 ] 0
|
|
XI_U PUTO_SHARERS [0 ] 0
|
|
XI_U Exclusive_Unblock [0 ] 0
|
|
XI_U Memory_Ack [0 ] 0
|
|
XI_U DMA_READ [0 ] 0
|
|
XI_U DMA_WRITE [0 ] 0
|
|
|
|
OI_D GETX [0 ] 0
|
|
OI_D GETS [0 ] 0
|
|
OI_D PUTX [0 ] 0
|
|
OI_D PUTO [0 ] 0
|
|
OI_D PUTO_SHARERS [0 ] 0
|
|
OI_D DMA_READ [0 ] 0
|
|
OI_D DMA_WRITE [0 ] 0
|
|
OI_D Data [0 ] 0
|
|
|
|
OD GETX [0 ] 0
|
|
OD GETS [0 ] 0
|
|
OD PUTX [0 ] 0
|
|
OD PUTO [0 ] 0
|
|
OD PUTO_SHARERS [0 ] 0
|
|
OD DMA_READ [0 ] 0
|
|
OD DMA_WRITE [0 ] 0
|
|
OD DMA_ACK [0 ] 0
|
|
|
|
MD GETX [0 ] 0
|
|
MD GETS [0 ] 0
|
|
MD PUTX [0 ] 0
|
|
MD PUTO [0 ] 0
|
|
MD PUTO_SHARERS [0 ] 0
|
|
MD DMA_READ [0 ] 0
|
|
MD DMA_WRITE [0 ] 0
|
|
MD DMA_ACK |