cf0e202cba
src/arch/sparc/isa/decoder.isa:
add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
fix O0-O5 operands registers
util/m5/Makefile.sparc:
Make sparc makefile compile a 64bit binary
util/m5/m5.c:
readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
implement readfile and debugbreak
--HG--
extra : convert_revision : 139b3f480ee6342b37b5642e072c8486d91a3944
154 lines
3.3 KiB
ArmAsm
154 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Ali Saidi
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*/
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#define m5_op 0x2
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#define m5_op3 0x37
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#include "m5ops.h"
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#define INST(func, rs1, rs2, rd) \
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.long (m5_op) << 30 | (rd) << 25 | (m5_op3) << 19 | (func) << 7 | \
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(rs1) << 14 | (rs2) << 0;
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#define LEAF(func) \
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.section ".text"; \
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.align 4; \
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.global func; \
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.type func, #function; \
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func:
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#define END(func) \
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.size func, (.-func)
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#define DEBUGBREAK INST(debugbreak_func, 0, 0, 0)
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#define M5EXIT INST(exit_func, 0, 0, 0)
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#define PANIC INST(panic_func, 0, 0, 0)
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#define READFILE INST(readfile_func, 0, 0, 0)
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LEAF(m5_exit)
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retl
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M5EXIT
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END(m5_exit)
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LEAF(m5_panic)
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retl
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PANIC
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END(m5_panic)
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LEAF(m5_readfile)
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retl
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READFILE
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END(m5_readfile)
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LEAF(m5_debugbreak)
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retl
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DEBUGBREAK
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END(m5_debugbreak)
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/* !!!!!! All code below here just panics !!!!!! */
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LEAF(arm)
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retl
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PANIC
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END(arm)
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LEAF(quiesce)
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retl
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PANIC
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END(quiesce)
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LEAF(quiesceNs)
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retl
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PANIC
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END(quiesceNs)
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LEAF(quiesceCycle)
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retl
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PANIC
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END(quiesceCycle)
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LEAF(quiesceTime)
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retl
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PANIC
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END(quiesceTime)
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LEAF(m5_initparam)
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retl
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PANIC
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END(m5_initparam)
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LEAF(m5_loadsymbol)
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retl
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PANIC
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END(m5_loadsymbol)
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LEAF(m5_reset_stats)
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retl
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PANIC
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END(m5_reset_stats)
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LEAF(m5_dump_stats)
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retl
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PANIC
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END(m5_dump_stats)
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LEAF(m5_dumpreset_stats)
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retl
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PANIC
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END(m5_dumpreset_stats)
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LEAF(m5_checkpoint)
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retl
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PANIC
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END(m5_checkpoint)
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LEAF(m5_switchcpu)
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retl
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PANIC
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END(m5_switchcpu)
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LEAF(m5_addsymbol)
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retl
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PANIC
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END(m5_addsymbol)
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LEAF(m5_anbegin)
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retl
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PANIC
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END(m5_anbegin)
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LEAF(m5_anwait)
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retl
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PANIC
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END(m5_anwait)
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