gem5/util/cpt_upgraders/remove-arm-cpsr-mode-miscreg.py
Curtis Dunham 87b9da2df4 sim: tag-based checkpoint versioning
This commit addresses gem5 checkpoints' linear versioning bottleneck.
Since development is distributed across many private trees, there exists
a sort of 'race' for checkpoint version numbers: internally a checkpoint
version may be used but then resynchronizing with the external tree causes
a conflict on that version.  This change replaces the linear version number
with a set of unique strings called tags.  Now the only conflicts that can
arise are of tag names, where collisions are much easier to avoid.

The checkpoint upgrader (util/cpt_upgrader.py) upgrades the version
representation, as one would expect. Each tag version implements its
upgrader code in a python file in the util/cpt_upgraders directory
rather than adding a function to the upgrader script itself.

The version tags are stored in the 'Globals' section rather than 'root'
(as the version was previously) because 'Globals' gets unserialized
first and can provide a warning before any other unserialization errors
can occur.
2015-09-02 15:23:30 -05:00

14 lines
495 B
Python

# Remove the MISCREG_CPSR_MODE register from the ARM register file
def upgrader(cpt):
if cpt.get('root','isa') == 'arm':
for sec in cpt.sections():
import re
# Search for all ISA sections
if re.search('.*sys.*\.cpu.*\.isa$', sec):
mr = cpt.get(sec, 'miscRegs').split()
# Remove MISCREG_CPSR_MODE
del mr[137]
cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
legacy_version = 5