87b9da2df4
This commit addresses gem5 checkpoints' linear versioning bottleneck. Since development is distributed across many private trees, there exists a sort of 'race' for checkpoint version numbers: internally a checkpoint version may be used but then resynchronizing with the external tree causes a conflict on that version. This change replaces the linear version number with a set of unique strings called tags. Now the only conflicts that can arise are of tag names, where collisions are much easier to avoid. The checkpoint upgrader (util/cpt_upgrader.py) upgrades the version representation, as one would expect. Each tag version implements its upgrader code in a python file in the util/cpt_upgraders directory rather than adding a function to the upgrader script itself. The version tags are stored in the 'Globals' section rather than 'root' (as the version was previously) because 'Globals' gets unserialized first and can provide a warning before any other unserialization errors can occur.
66 lines
2.6 KiB
Python
66 lines
2.6 KiB
Python
# The ISA is now a separate SimObject, which means that we serialize
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# it in a separate section instead of as a part of the ThreadContext.
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def upgrader(cpt):
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isa = cpt.get('root','isa')
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isa_fields = {
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"alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ),
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"arm" : ( "miscRegs" ),
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"sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",
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"stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt",
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"tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate",
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"htstate", "hintp", "htba", "hstick_cmpr",
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"strandStatusReg", "fsr", "priContext", "secContext",
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"partId", "lsuCtrlReg", "scratchPad",
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"cpu_mondo_head", "cpu_mondo_tail",
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"dev_mondo_head", "dev_mondo_tail",
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"res_error_head", "res_error_tail",
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"nres_error_head", "nres_error_tail",
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"tick_intr_sched",
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"cpu", "tc_num", "tick_cmp", "stick_cmp", "hstick_cmp"),
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"x86" : ( "regVal" ),
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}
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isa_fields = isa_fields.get(isa, [])
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isa_sections = []
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for sec in cpt.sections():
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import re
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re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec)
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# Search for all the execution contexts
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if not re_cpu_match:
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continue
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if re_cpu_match.group(2) != "0":
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# This shouldn't happen as we didn't support checkpointing
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# of in-order and O3 CPUs.
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raise ValueError("Don't know how to migrate multi-threaded CPUs "
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"from version 1")
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isa_section = []
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for fspec in isa_fields:
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for (key, value) in cpt.items(sec, raw=True):
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if key in isa_fields:
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isa_section.append((key, value))
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name = "%s.isa" % re_cpu_match.group(1)
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isa_sections.append((name, isa_section))
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for (key, value) in isa_section:
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cpt.remove_option(sec, key)
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for (sec, options) in isa_sections:
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# Some intermediate versions of gem5 have empty ISA sections
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# (after we made the ISA a SimObject, but before we started to
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# serialize into a separate ISA section).
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if not cpt.has_section(sec):
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cpt.add_section(sec)
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else:
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if cpt.items(sec):
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raise ValueError("Unexpected populated ISA section in old "
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"checkpoint")
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for (key, value) in options:
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cpt.set(sec, key, value)
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legacy_version = 4
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